Horácio Cláudio de Campos Neto
AuthID: R-000-5ZS
31
TITLE: Parallel dot-products for deep learning on FPGA
AUTHORS: Vestias, M; Duarte, RP; De Sousa, JT; Neto, H;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications, FPL 2017 in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
AUTHORS: Vestias, M; Duarte, RP; De Sousa, JT; Neto, H;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications, FPL 2017 in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
32
TITLE: Parallel Dot-Products for Deep Learning on FPGA
AUTHORS: Mario Vestias; Rui Policarpo Duarte; Jose T de Sousa; Horacio Neto;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications (FPL) in 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
AUTHORS: Mario Vestias; Rui Policarpo Duarte; Jose T de Sousa; Horacio Neto;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications (FPL) in 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
INDEXED IN: 
WOS
WOS33
TITLE: Multi-core for K-means clustering on FPGA
AUTHORS: Canilho, J; Véstias, M; Neto, H;
PUBLISHED: 2016, SOURCE: 26th International Conference on Field-Programmable Logic and Applications, FPL 2016 in FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications
AUTHORS: Canilho, J; Véstias, M; Neto, H;
PUBLISHED: 2016, SOURCE: 26th International Conference on Field-Programmable Logic and Applications, FPL 2016 in FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications
34
TITLE: XtokaxtikoX: A Stochastic Computing-Based Autonomous Cyber-Physical System
AUTHORS: Duarte, RP; Neto, H; Vestias, M;
PUBLISHED: 2016, SOURCE: IEEE International Conference on Rebooting Computing (ICRC) in 2016 IEEE INTERNATIONAL CONFERENCE ON REBOOTING COMPUTING (ICRC)
AUTHORS: Duarte, RP; Neto, H; Vestias, M;
PUBLISHED: 2016, SOURCE: IEEE International Conference on Rebooting Computing (ICRC) in 2016 IEEE INTERNATIONAL CONFERENCE ON REBOOTING COMPUTING (ICRC)
35
TITLE: Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication
AUTHORS: Jose, WM; Silva, AR; Vestias, MP; Neto, HC;
PUBLISHED: 2015, SOURCE: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, VOLUME: 82, ISSUE: 1
AUTHORS: Jose, WM; Silva, AR; Vestias, MP; Neto, HC;
PUBLISHED: 2015, SOURCE: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, VOLUME: 82, ISSUE: 1
INDEXED IN: 
Scopus WOS
Scopus WOS IN MY: 
ORCID
ORCID36
TITLE: Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions
AUTHORS: Victor M G Goncalves Martins; Joao Gabriel Reis; Horacio C C Neto; Eduardo Augusto Bezerra;
PUBLISHED: 2015, SOURCE: 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) in 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
AUTHORS: Victor M G Goncalves Martins; Joao Gabriel Reis; Horacio C C Neto; Eduardo Augusto Bezerra;
PUBLISHED: 2015, SOURCE: 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) in 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
37
TITLE: A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow
AUTHORS: Victor M G Goncalves Martins; Paulo R C Villa; Horacio C C Neto; Eduardo Augusto Bezerra;
PUBLISHED: 2015, SOURCE: IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI) in 2015 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, VOLUME: 07-10-July-2015
AUTHORS: Victor M G Goncalves Martins; Paulo R C Villa; Horacio C C Neto; Eduardo Augusto Bezerra;
PUBLISHED: 2015, SOURCE: IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI) in 2015 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, VOLUME: 07-10-July-2015
38
TITLE: A Many-Core Co-Processor for Embedded Parallel Computing on FPGA
AUTHORS: Wilson Jose; Horacio Neto; Mario Vestias;
PUBLISHED: 2015, SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTHORS: Wilson Jose; Horacio Neto; Mario Vestias;
PUBLISHED: 2015, SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
39
TITLE: Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture
AUTHORS: Joao Pinhao; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLISHED: 2015, SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTHORS: Joao Pinhao; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLISHED: 2015, SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
40
TITLE: Enhancing stochastic computations via process variation
AUTHORS: Duarte, RP; Véstias, M; Neto, H;
PUBLISHED: 2015, SOURCE: 25th International Conference on Field Programmable Logic and Applications, FPL 2015 in 25th International Conference on Field Programmable Logic and Applications, FPL 2015
AUTHORS: Duarte, RP; Véstias, M; Neto, H;
PUBLISHED: 2015, SOURCE: 25th International Conference on Field Programmable Logic and Applications, FPL 2015 in 25th International Conference on Field Programmable Logic and Applications, FPL 2015
