Horácio Cláudio de Campos Neto
AuthID: R-000-5ZS
41
TITLE: FPGA Redundancy Recovery based on Partial Bitstreams for Multiple Partitions
AUTHORS: Victor M G Goncalves Martins; Joao Gabriel Reis; Horacio C C Neto; Eduardo Augusto Bezerra;
PUBLISHED: 2015, SOURCE: 16th IEEE Latin American Test Symposium (LATS) in 2015 16TH LATIN-AMERICAN TEST SYMPOSIUM (LATS)
AUTHORS: Victor M G Goncalves Martins; Joao Gabriel Reis; Horacio C C Neto; Eduardo Augusto Bezerra;
PUBLISHED: 2015, SOURCE: 16th IEEE Latin American Test Symposium (LATS) in 2015 16TH LATIN-AMERICAN TEST SYMPOSIUM (LATS)
INDEXED IN: 
WOS
WOS42
TITLE: Enhancing Stochastic Computations via Process Variation
AUTHORS: Rui Policarpo Duarte; Mario Vestias; Horacio Neto;
PUBLISHED: 2015, SOURCE: 25th International Conference on Field Programmable Logic and Applications in 2015 25TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
AUTHORS: Rui Policarpo Duarte; Mario Vestias; Horacio Neto;
PUBLISHED: 2015, SOURCE: 25th International Conference on Field Programmable Logic and Applications in 2015 25TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
INDEXED IN: WOS
WOS43
TITLE: Efficient implementation of a single-precision floating-point arithmetic unit on FPGA
AUTHORS: Jose, W; Silva, AR; Neto, H; Vestias, M;
PUBLISHED: 2014, SOURCE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
AUTHORS: Jose, W; Silva, AR; Neto, H; Vestias, M;
PUBLISHED: 2014, SOURCE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
44
TITLE: Trends of CPU, GPU and FPGA for high-performance computing
AUTHORS: Vestias, M; Neto, H;
PUBLISHED: 2014, SOURCE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
AUTHORS: Vestias, M; Neto, H;
PUBLISHED: 2014, SOURCE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
45
TITLE: Modeling and Simulation of a Many-Core Architecture Using SystemC
AUTHORS: Ana Rita Silva; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLISHED: 2014, SOURCE: 2nd Conference on Electronics, Telecommunications, and Computers (CETC) in CONFERENCE ON ELECTRONICS, TELECOMMUNICATIONS AND COMPUTERS - CETC 2013, VOLUME: 17
AUTHORS: Ana Rita Silva; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLISHED: 2014, SOURCE: 2nd Conference on Electronics, Telecommunications, and Computers (CETC) in CONFERENCE ON ELECTRONICS, TELECOMMUNICATIONS AND COMPUTERS - CETC 2013, VOLUME: 17
INDEXED IN: WOS 
CrossRef
WOS CrossRef46
TITLE: Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication
AUTHORS: Wilson M José; Ana Rita Silva; Mário P Véstias; Horácio C Neto;
PUBLISHED: 2014, SOURCE: Analog Integrated Circuits and Signal Processing - Analog Integr Circ Sig Process, VOLUME: 82, ISSUE: 1
AUTHORS: Wilson M José; Ana Rita Silva; Mário P Véstias; Horácio C Neto;
PUBLISHED: 2014, SOURCE: Analog Integrated Circuits and Signal Processing - Analog Integr Circ Sig Process, VOLUME: 82, ISSUE: 1
47
TITLE: Very low resource table-based FPGA evaluation of elementary functions
AUTHORS: Neto, HC; Vestias, MP;
PUBLISHED: 2013, SOURCE: 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013 in 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013
AUTHORS: Neto, HC; Vestias, MP;
PUBLISHED: 2013, SOURCE: 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013 in 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013
48
TITLE: Analysis of matrix multiplication on high density Virtex-7 FPGA
AUTHORS: Jose, W; Silva, AR; Neto, H; Vestias, M;
PUBLISHED: 2013, SOURCE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
AUTHORS: Jose, W; Silva, AR; Neto, H; Vestias, M;
PUBLISHED: 2013, SOURCE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
49
TITLE: A reconfigurable computing architecture using magnetic tunneling junction memories
AUTHORS: Silva, V; Fernandes, J; Vestias, M; Neto, H;
PUBLISHED: 2013, SOURCE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
AUTHORS: Silva, V; Fernandes, J; Vestias, M; Neto, H;
PUBLISHED: 2013, SOURCE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
50
TITLE: Decimal division using the newton-raphson method and radix-1000 arithmetic
AUTHORS: Vestias, MP; Neto, HC;
PUBLISHED: 2013, SOURCE: Embedded Systems Design with FPGAs
AUTHORS: Vestias, MP; Neto, HC;
PUBLISHED: 2013, SOURCE: Embedded Systems Design with FPGAs
INDEXED IN: 
Scopus
Scopus IN MY: 
ORCID
ORCID