José Carlos Alves Pereira Monteiro
AuthID: R-000-85F
31
TITLE: Analysis of the Conditions for Worst Case Switching Activity in Integrated Circuits
AUTHORS: Carlos Sampaio; Jose Monteiro; Silveira, L. Miguel;
PUBLISHED: 2010, SOURCE: 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2010 FIRST IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)
AUTHORS: Carlos Sampaio; Jose Monteiro; Silveira, L. Miguel;
PUBLISHED: 2010, SOURCE: 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2010 FIRST IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)
INDEXED IN: 
WOS
WOS32
TITLE: A New Quaternary FPGA Based on a Voltage-mode Multi-valued Circuit
AUTHORS: Cristiano Lazzari; Paulo Flores; Jose Monteiro; Luigi Carro;
PUBLISHED: 2010, SOURCE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010)
AUTHORS: Cristiano Lazzari; Paulo Flores; Jose Monteiro; Luigi Carro;
PUBLISHED: 2010, SOURCE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010)
INDEXED IN: WOS
WOS33
TITLE: Integrated Circuit and System Design : Power and Timing Modeling, Optimization and Simulation. 19th International Workshop, PATMOS 2009, Delft, the Netherlands, September 9-11, 2009, Revised Selected Papers
AUTHORS: José Monteiro; Rene van Leuken;
PUBLISHED: 2010
AUTHORS: José Monteiro; Rene van Leuken;
PUBLISHED: 2010
INDEXED IN: 
Openlibrary
Openlibrary34
TITLE: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
AUTHORS: Lars Svensson; José Monteiro;
PUBLISHED: 2009, SOURCE: Lecture Notes in Computer Science
AUTHORS: Lars Svensson; José Monteiro;
PUBLISHED: 2009, SOURCE: Lecture Notes in Computer Science
35
TITLE: Efficient Dedicated Multiplication Blocks for 2's Complement Radix-16 and Radix-256 Array Multipliers
AUTHORS: Leandro Zafalon Pieper; Eduardo A C da Costa; Sergio J M de Almeida; Sergio Bampi; Jose C Monteiro;
PUBLISHED: 2008, SOURCE: 2nd International Conference on Signals, Circuits and Systems in SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS
AUTHORS: Leandro Zafalon Pieper; Eduardo A C da Costa; Sergio J M de Almeida; Sergio Bampi; Jose C Monteiro;
PUBLISHED: 2008, SOURCE: 2nd International Conference on Signals, Circuits and Systems in SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS
INDEXED IN: WOS
WOS36
TITLE: A comparison of layout implementations of pipelined and non-pipelined signed radix-4 array multiplier and modified booth multiplier architectures
AUTHORS: Leonardo L de Oliveira; Cristiano Santos; Daniel Ferrao; Eduardo Costa; Jose Monteiro; Joao Baptista Martins; Sergio Bampi; Ricardo Reis;
PUBLISHED: 2007, SOURCE: 13th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005) in VLSI-SOC: FROM SYSTEMS TO SILICON, VOLUME: 240
AUTHORS: Leonardo L de Oliveira; Cristiano Santos; Daniel Ferrao; Eduardo Costa; Jose Monteiro; Joao Baptista Martins; Sergio Bampi; Ricardo Reis;
PUBLISHED: 2007, SOURCE: 13th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005) in VLSI-SOC: FROM SYSTEMS TO SILICON, VOLUME: 240
INDEXED IN: WOS
WOS37
TITLE: Gray encoded arithmetic operators applied to FFT and FIR dedicated datapaths
AUTHORS: Eduardo A C da Costa; Jose C Monteiro; Sergio Bampi;
PUBLISHED: 2006, SOURCE: 12th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003) in VLSI-SOC: FROM SYSTEMS TO CHIPS, VOLUME: 200
AUTHORS: Eduardo A C da Costa; Jose C Monteiro; Sergio Bampi;
PUBLISHED: 2006, SOURCE: 12th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003) in VLSI-SOC: FROM SYSTEMS TO CHIPS, VOLUME: 200
INDEXED IN: WOS
WOS38
TITLE: Precomputation-based Sequential Logic Optimization For Low Power
AUTHORS: Alidina, M; Monteiro, J; Devadas, S; Ghosh, A; Papefthymiou, M;
PUBLISHED: 2005, SOURCE: IEEE/ACM International Conference on Computer-Aided Design
AUTHORS: Alidina, M; Monteiro, J; Devadas, S; Ghosh, A; Papefthymiou, M;
PUBLISHED: 2005, SOURCE: IEEE/ACM International Conference on Computer-Aided Design
39
TITLE: Low Power Architectures for FFT and FIR Dedicated Datapaths
AUTHORS: Costa, E; Bampi, S; Monteiro, J;
PUBLISHED: 2003, SOURCE: 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 in Midwest Symposium on Circuits and Systems, VOLUME: 3
AUTHORS: Costa, E; Bampi, S; Monteiro, J;
PUBLISHED: 2003, SOURCE: 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 in Midwest Symposium on Circuits and Systems, VOLUME: 3
40
TITLE: Optimization of combinational and sequential logic circuits for low power using precomputation
AUTHORS: Monteiro, J; Rinderknecht, J; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings Sixteenth Conference on Advanced Research in VLSI
AUTHORS: Monteiro, J; Rinderknecht, J; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings Sixteenth Conference on Advanced Research in VLSI
