Leonel Augusto Pires Seabra Sousa
AuthID: R-000-93B
181
TITLE: Accelerating the phylogenetic parsimony function on heterogeneous systems
AUTHORS: Sergio Santander Jiménez; Aleksandar Ilic; Leonel Sousa; Miguel A Vega Rodríguez;
PUBLISHED: 2017, SOURCE: Concurrency and Computation: Practice and Experience, VOLUME: 29, ISSUE: 8
AUTHORS: Sergio Santander Jiménez; Aleksandar Ilic; Leonel Sousa; Miguel A Vega Rodríguez;
PUBLISHED: 2017, SOURCE: Concurrency and Computation: Practice and Experience, VOLUME: 29, ISSUE: 8
182
TITLE: On Boosting Energy-Efficiency of Heterogeneous Embedded Systems via Game Theory
AUTHORS: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLISHED: 2017, SOURCE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
AUTHORS: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLISHED: 2017, SOURCE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
184
TITLE: Parallel Programming Framework for H.264/AVC Video Encoding in Multicore Systems
AUTHORS: Roma, N; Rodrigues, A; Sousa, L;
PUBLISHED: 2017, SOURCE: Programming Multicore and Many-Core Computing Systems
AUTHORS: Roma, N; Rodrigues, A; Sousa, L;
PUBLISHED: 2017, SOURCE: Programming Multicore and Many-Core Computing Systems
185
TITLE: A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo 2<i><SUP>n</SUP></i>+1 Multiplier
AUTHORS: Mirhosseini, SM; Molahosseini, AS; Hosseinzadeh, M; Sousa, L; Martins, P;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 64, ISSUE: 7
AUTHORS: Mirhosseini, SM; Molahosseini, AS; Hosseinzadeh, M; Sousa, L; Martins, P;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 64, ISSUE: 7
186
TITLE: Exploring GPU performance, power and energy-efficiency bounds with Cache-aware Roofline Modeling
AUTHORS: Andre Lopes; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: 2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017
AUTHORS: Andre Lopes; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: 2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017
187
TITLE: Cache-aware Roofline Model in Intel® Advisor
AUTHORS: Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: ERCIM News, VOLUME: 2017, ISSUE: 110
AUTHORS: Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: ERCIM News, VOLUME: 2017, ISSUE: 110
INDEXED IN: 
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DBLP188
TITLE: Efficient reductions in cyclotomic rings - Application to R-LWE based FHE schemes
AUTHORS: Jean Claude Bajard; Julien Eynard; Anwar Hasan; Paulo Martins; Leonel Sousa; Vincent Zucca;
PUBLISHED: 2017, SOURCE: IACR Cryptology ePrint Archive, VOLUME: 2017
AUTHORS: Jean Claude Bajard; Julien Eynard; Anwar Hasan; Paulo Martins; Leonel Sousa; Vincent Zucca;
PUBLISHED: 2017, SOURCE: IACR Cryptology ePrint Archive, VOLUME: 2017
INDEXED IN: DBLP
DBLP IN MY: DBLP
DBLP189
TITLE: A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo 2n + 1 Multiplier
AUTHORS: Seyed Mostafa Mirhosseini; Amir Sabbagh Molahosseini; Mehdi Hosseinzadeh; Leonel Sousa; Paulo Martins;
PUBLISHED: 2017, SOURCE: IEEE Trans. on Circuits and Systems, VOLUME: 64, ISSUE: 7
AUTHORS: Seyed Mostafa Mirhosseini; Amir Sabbagh Molahosseini; Mehdi Hosseinzadeh; Leonel Sousa; Paulo Martins;
PUBLISHED: 2017, SOURCE: IEEE Trans. on Circuits and Systems, VOLUME: 64, ISSUE: 7
INDEXED IN: DBLP
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DBLP190
TITLE: Performance Analysis with Cache-Aware Roofline Model in Intel Advisor
AUTHORS: Diogo Marques; Helder Duarte; Aleksandar Ilic; Leonel Sousa; Roman Belenov; Philippe Thierry; Zakhar A Matveev;
PUBLISHED: 2017, SOURCE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
AUTHORS: Diogo Marques; Helder Duarte; Aleksandar Ilic; Leonel Sousa; Roman Belenov; Philippe Thierry; Zakhar A Matveev;
PUBLISHED: 2017, SOURCE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXED IN: DBLP
DBLP IN MY: DBLP
DBLP