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A Universal Architecture for Designing Efficient Modulo 2(N),+1 Multipliers
AuthID
P-000-30X
2
Author(s)
Sousa, L
·
Chaves, R
Document Type
Article
Year published
2005
Published
in
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,
ISSN: 1549-8328
Volume: 52, Issue: 6, Pages: 1166-1178 (13)
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/en/publications/view/3101
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Publication Identifiers
DOI
:
10.1109/tcsi.2005.849143
DBLP
: journals/tcas/SousaC05
SCOPUS
: 2-s2.0-22144485617
Wos
: WOS:000229818800014
Source Identifiers
ISSN
: 1549-8328
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