Publications

Area-Delay-Power-Aware Adder Placement Method for Rns Reverse Converter Design

AuthID
P-00K-WW2

Author(s)

Zarandi, AAE

Molahosseini, AS

Sousa, L

Hosseinzadeh, M

Navi, K

Editor(s)

Julian, P; Andreou, AG

Document Type

Proceedings Paper

Year published

2016

Published

in 2016 IEEE 7TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS) in IEEE Latin American Symposium on Circuits and Systems, ISSN: 2330-9954

Pages: 223-226 (4)

Conference

7Th Ieee Latin American Symposium on Circuits and Systems (Lascas), Date: FEB 28-MAR 02, 2016, Location: Florianopolis, BRAZIL, Sponsors: IEEE, Univ Fed Santa Catarina, MentorGraphics, Creat Solut, Macnica DHW, Synopsys, imec

Indexing

Wos^®

Dblp^®/en/publications/view/652162

Crossref^®

Google Scholar^®

Metadata
Sources

Publication Identifiers

DOI: 10.1109/LASCAS.2016.7451050

DBLP: conf/lascas/ZarandiMSHN16

Wos: WOS:000381984000048

Source Identifiers

ISSN: 2330-9954

Export Publication Metadata

Marked List

Add to Marked List

Info

At this moment we don't have any links to full text documens.

Area-Delay-Power-Aware Adder Placement Method for Rns Reverse Converter Design

Useful Links

Get Help

Federated Authentication (Click on the image)

Area-Delay-Power-Aware Adder Placement Method for Rns Reverse Converter Design

Useful Links

Get Help