Publications

Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems

AuthID
P-00S-CQ5

Author(s)

Rashid, SA

Nelissen, G

Tovar, E

Editor(s)

DiNatale,G;Bolchini,C;Vatajelu,EI

Document Type

Proceedings Paper

Year published

2020

Published

in PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020) in Design Automation and Test in Europe Conference and Exhibition, ISSN: 1530-1591

Pages: 442-447 (6)

Conference

Design, Automation and Test in Europe Conference and Exhibition (Date), Date: MAR 09-13, 2020, Location: Grenoble, FRANCE, Sponsors: European Design & Automat Assoc, SEMI Strateg Technol Community & Elect Syst Design Alliance, IEEE Council Elect Design Automat, European Elect Chips & Syst Design Initiat, ACM Special Interest Grp Design Automat, Russian Acad Sci, IEEE Comp Soc, Test Technol Tech Council, IEEE Solid State Circuits Soc, Int Federat Informat Proc, Grenoble INP, Inria, Autonomous Intelligent Driving, Cadence, List Ceatech, Leti Ceatech, Univ Grenoble Alpes, Cybersecur Inst, Hisilicon, IEEE Council Elect Design Automat, Intel, NanoElec, Mentor Graph, ST, Synopsys

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