Nuno Cavaco Gomes Horta


AuthID: R-000-DMG

Publicações Confirmadas: 270



91
TÍTULO: New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization
AUTORES: Lourenco, N ; Martins, R; Povoa, R; Canelas, A; Horta, N ; Passos, F; Castro Lopez, R; Roca, E; Fernandez, FV;
PUBLICAÇÃO: 2017, FONTE: 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 in SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
INDEXADO EM: Scopus CrossRef
NO MEU: ORCID
92
TÍTULO: Related Work
AUTORES: João Leitão; Rui Ferreira Neves; Nuno C G Horta ;
PUBLICAÇÃO: 2017, FONTE: Identifying Patterns in Financial Markets - SpringerBriefs in Applied Sciences and Technology
INDEXADO EM: CrossRef
NO MEU: ORCID
93
TÍTULO: Stochastic-based placement template generator for analog IC layout-aware synthesis
AUTORES: Martins, R; Lourenço, N ; Canelas, A; Horta, N ;
PUBLICAÇÃO: 2017, FONTE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 58
INDEXADO EM: Scopus WOS CrossRef
NO MEU: ORCID
94
TÍTULO: Systematic design of a voltage controlled oscillator using a layout-aware approach
AUTORES: Passos, F; Roca, E; Castro Lopez, R; Fernandez, FV; Martins, R; Lourenco, N ; Povoa, R; Canelas, A; Horta, N ;
PUBLICAÇÃO: 2017, FONTE: 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 in SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
INDEXADO EM: Scopus CrossRef
NO MEU: ORCID
95
TÍTULO: Using Sentiment from Twitter optimized by Genetic Algorithms to Predict the Stock Marke
AUTORES: Simoes, C; Neves, R; Horta, N ;
PUBLICAÇÃO: 2017, FONTE: IEEE Congress on Evolutionary Computation (CEC) in 2017 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION (CEC)
INDEXADO EM: Scopus WOS CrossRef: 2
NO MEU: ORCID
96
TÍTULO: AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation  Full Text
AUTORES: Nuno Lourenco ; Ricardo Martins ; Antonio Canelas; Ricardo Povoa; Nuno Horta ;
PUBLICAÇÃO: 2016, FONTE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 55
INDEXADO EM: Scopus WOS CrossRef: 16
NO MEU: ORCID
97
TÍTULO: An 8bit Logarithmic AD Converter Using Cross-Coupled Inverters and a Time-to-Digital Converter
AUTORES: Santos, M; Horta, N ; Guilherme, J;
PUBLICAÇÃO: 2016, FONTE: 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) in 2016 12TH CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME)
INDEXADO EM: Scopus WOS CrossRef
NO MEU: ORCID
98
TÍTULO: Analog integrated circuit design automation: Placement, routing and parasitic extraction techniques
AUTORES: Martins, R; Lourenço, N; Horta, N ;
PUBLICAÇÃO: 2016, FONTE: Analog Integrated Circuit Design Automation: Placement, Routing and Parasitic Extraction Techniques
INDEXADO EM: Scopus CrossRef
NO MEU: ORCID
99
TÍTULO: Automated Analog IC Design Constraints Generation for a Layout-Aware Sizing Approach
AUTORES: Andre Ferreira; Nuno Lourenco ; Ricardo Martins; Nuno Horta ;
PUBLICAÇÃO: 2016, FONTE: 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) in 2016 13TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD)
INDEXADO EM: Scopus WOS CrossRef
NO MEU: ORCID
100
TÍTULO: Automatic analog IC sizing and optimization constrained with PVT corners and layout effects
AUTORES: Lourenço, N ; Martins, R; Horta, N ;
PUBLICAÇÃO: 2016, FONTE: Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
INDEXADO EM: Scopus CrossRef
NO MEU: ORCID
Página 10 de 27. Total de resultados: 270.

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