Mário Pereira Véstias
AuthID: R-000-CZ3
81
TÃTULO: RF FRONT END RECEIVER FOR GPS/GALILEO L1/E1
AUTORES: Filipe Palhinha; Ricardo Pereira; Duarte Carona; Antonio Serrador; Mario Vestias; Joao Silva; Tiago Peres; Pedro Silva;
PUBLICAÇÃO: 2014, FONTE: 2nd Conference on Electronics, Telecommunications, and Computers (CETC) in CONFERENCE ON ELECTRONICS, TELECOMMUNICATIONS AND COMPUTERS - CETC 2013, VOLUME: 17
AUTORES: Filipe Palhinha; Ricardo Pereira; Duarte Carona; Antonio Serrador; Mario Vestias; Joao Silva; Tiago Peres; Pedro Silva;
PUBLICAÇÃO: 2014, FONTE: 2nd Conference on Electronics, Telecommunications, and Computers (CETC) in CONFERENCE ON ELECTRONICS, TELECOMMUNICATIONS AND COMPUTERS - CETC 2013, VOLUME: 17
82
TÃTULO: Modeling and Simulation of a Many-Core Architecture Using SystemC
AUTORES: Ana Rita Silva; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLICAÇÃO: 2014, FONTE: 2nd Conference on Electronics, Telecommunications, and Computers (CETC) in CONFERENCE ON ELECTRONICS, TELECOMMUNICATIONS AND COMPUTERS - CETC 2013, VOLUME: 17
AUTORES: Ana Rita Silva; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLICAÇÃO: 2014, FONTE: 2nd Conference on Electronics, Telecommunications, and Computers (CETC) in CONFERENCE ON ELECTRONICS, TELECOMMUNICATIONS AND COMPUTERS - CETC 2013, VOLUME: 17
83
TÃTULO: Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication
AUTORES: Wilson M José; Ana Rita Silva; Mário P Véstias; Horácio C Neto;
PUBLICAÇÃO: 2014, FONTE: Analog Integrated Circuits and Signal Processing - Analog Integr Circ Sig Process, VOLUME: 82, NÚMERO: 1
AUTORES: Wilson M José; Ana Rita Silva; Mário P Véstias; Horácio C Neto;
PUBLICAÇÃO: 2014, FONTE: Analog Integrated Circuits and Signal Processing - Analog Integr Circ Sig Process, VOLUME: 82, NÚMERO: 1
84
TÃTULO: FPGA-based architecture for hyperspectral endmember extraction
AUTORES: João Rosário; José M P Nascimento; Mário Véstias;
PUBLICAÇÃO: 2014, FONTE: High-Performance Computing in Remote Sensing IV, VOLUME: 9247
AUTORES: João Rosário; José M P Nascimento; Mário Véstias;
PUBLICAÇÃO: 2014, FONTE: High-Performance Computing in Remote Sensing IV, VOLUME: 9247
85
TÃTULO: A many-core overlay for high performance embedded computing on FPGAS
AUTORES: Mário Véstias; Horácio Neto;
PUBLICAÇÃO: 2014, FONTE: 1st International Workshop on FPGAs for Software Programmers (FSP 2014)
AUTORES: Mário Véstias; Horácio Neto;
PUBLICAÇÃO: 2014, FONTE: 1st International Workshop on FPGAs for Software Programmers (FSP 2014)
INDEXADO EM: 
Handle
Handle86
TÃTULO: Very low resource table-based FPGA evaluation of elementary functions
AUTORES: Neto, HC; Vestias, MP;
PUBLICAÇÃO: 2013, FONTE: 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013 in 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013
AUTORES: Neto, HC; Vestias, MP;
PUBLICAÇÃO: 2013, FONTE: 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013 in 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013
87
TÃTULO: Analysis of matrix multiplication on high density Virtex-7 FPGA
AUTORES: Jose, W; Silva, AR; Neto, H; Vestias, M;
PUBLICAÇÃO: 2013, FONTE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
AUTORES: Jose, W; Silva, AR; Neto, H; Vestias, M;
PUBLICAÇÃO: 2013, FONTE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
88
TÃTULO: A reconfigurable computing architecture using magnetic tunneling junction memories
AUTORES: Silva, V; Fernandes, J; Vestias, M; Neto, H;
PUBLICAÇÃO: 2013, FONTE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
AUTORES: Silva, V; Fernandes, J; Vestias, M; Neto, H;
PUBLICAÇÃO: 2013, FONTE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
89
TÃTULO: Decimal division using the newton-raphson method and radix-1000 arithmetic
AUTORES: Vestias, MP; Neto, HC;
PUBLICAÇÃO: 2013, FONTE: Embedded Systems Design with FPGAs
AUTORES: Vestias, MP; Neto, HC;
PUBLICAÇÃO: 2013, FONTE: Embedded Systems Design with FPGAs
INDEXADO EM: 
Scopus
Scopus90
TÃTULO: Very low resource table-based FPGA evaluation of elementary functions
AUTORES: Horacio C Neto; Mario P Vestias;
PUBLICAÇÃO: 2013, FONTE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)
AUTORES: Horacio C Neto; Mario P Vestias;
PUBLICAÇÃO: 2013, FONTE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)
INDEXADO EM: 
WOS
WOS NO MEU: 
ORCID
ORCID