Aleksandar Ilic
AuthID: R-001-NJ1
51
TÃTULO: GPGPU Power Modeling for Multi-Domain Voltage-Frequency Scaling
AUTORES: Guerreiro, J; Ilic, A; Roma, N ; Tomas, P ;
PUBLICAÇÃO: 2018, FONTE: 24th IEEE International Symposium on High Performance Computer Architecture (HPCA) in 2018 24TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), VOLUME: 2018-February
AUTORES: Guerreiro, J; Ilic, A; Roma, N ; Tomas, P ;
PUBLICAÇÃO: 2018, FONTE: 24th IEEE International Symposium on High Performance Computer Architecture (HPCA) in 2018 24TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), VOLUME: 2018-February
52
TÃTULO: Path matrix and path energy of graphs PDF
AUTORES: Aleksandar Ilic; Milan Basic;
PUBLICAÇÃO: 2018, FONTE: CoRR, VOLUME: abs/1810.04870
AUTORES: Aleksandar Ilic; Milan Basic;
PUBLICAÇÃO: 2018, FONTE: CoRR, VOLUME: abs/1810.04870
INDEXADO EM: 
DBLP 
arXiv
DBLP arXiv NO MEU: DBLP
DBLP53
TÃTULO: Accelerating CNN computation: quantisation tuning and network resizing
AUTORES: Alexandre Vieira; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2018, FONTE: Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE@PACT 2018, Limassol, Cyprus, November 4, 2018
AUTORES: Alexandre Vieira; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2018, FONTE: Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE@PACT 2018, Limassol, Cyprus, November 4, 2018
INDEXADO EM: DBLP
DBLP NO MEU: DBLP
DBLP54
TÃTULO: Cache-Aware Roofline Model and Medical Image Processing Optimizations in GPUs
AUTORES: Estefania Serrano; Aleksandar Ilic; Leonel Sousa; Javier García Blas; Jesús Carretero;
PUBLICAÇÃO: 2018, FONTE: High Performance Computing - ISC High Performance 2018 International Workshops, Frankfurt/Main, Germany, June 28, 2018, Revised Selected Papers, VOLUME: 11203
AUTORES: Estefania Serrano; Aleksandar Ilic; Leonel Sousa; Javier García Blas; Jesús Carretero;
PUBLICAÇÃO: 2018, FONTE: High Performance Computing - ISC High Performance 2018 International Workshops, Frankfurt/Main, Germany, June 28, 2018, Revised Selected Papers, VOLUME: 11203
INDEXADO EM: DBLP
DBLP NO MEU: DBLP
DBLP56
TÃTULO: GPU Parallelization of HEVC In-Loop Filters
AUTORES: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben H H Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: International Journal of Parallel Programming, VOLUME: 45, NÚMERO: 6
AUTORES: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben H H Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: International Journal of Parallel Programming, VOLUME: 45, NÚMERO: 6
INDEXADO EM: 
Scopus DBLP
Scopus DBLP NO MEU: DBLP
DBLP57
TÃTULO: GHEVC: An Efficient HEVC Decoder for Graphics Processing Units Full Text
AUTORES: Diego F de Souza; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: IEEE TRANSACTIONS ON MULTIMEDIA, VOLUME: 19, NÚMERO: 3
AUTORES: Diego F de Souza; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: IEEE TRANSACTIONS ON MULTIMEDIA, VOLUME: 19, NÚMERO: 3
59
TÃTULO: Accelerating the phylogenetic parsimony function on heterogeneous systems
AUTORES: Sergio Santander Jiménez; Aleksandar Ilic; Leonel Sousa; Miguel A Vega Rodríguez;
PUBLICAÇÃO: 2017, FONTE: Concurrency and Computation: Practice and Experience, VOLUME: 29, NÚMERO: 8
AUTORES: Sergio Santander Jiménez; Aleksandar Ilic; Leonel Sousa; Miguel A Vega Rodríguez;
PUBLICAÇÃO: 2017, FONTE: Concurrency and Computation: Practice and Experience, VOLUME: 29, NÚMERO: 8
60
TÃTULO: On Boosting Energy-Efficiency of Heterogeneous Embedded Systems via Game Theory
AUTORES: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
AUTORES: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
