Aleksandar Ilic
AuthID: R-001-NJ1
61
TÃTULO: Accelerating the phylogenetic parsimony function on heterogeneous systems
AUTORES: Sergio Santander Jiménez; Aleksandar Ilic; Leonel Sousa; Miguel A Vega Rodríguez;
PUBLICAÇÃO: 2017, FONTE: Concurrency and Computation: Practice and Experience, VOLUME: 29, NÚMERO: 8
AUTORES: Sergio Santander Jiménez; Aleksandar Ilic; Leonel Sousa; Miguel A Vega Rodríguez;
PUBLICAÇÃO: 2017, FONTE: Concurrency and Computation: Practice and Experience, VOLUME: 29, NÚMERO: 8
62
TÃTULO: On Boosting Energy-Efficiency of Heterogeneous Embedded Systems via Game Theory
AUTORES: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
AUTORES: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
63
TÃTULO: Exploring GPU performance, power and energy-efficiency bounds with Cache-aware Roofline Modeling
AUTORES: Andre Lopes; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: 2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017
AUTORES: Andre Lopes; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: 2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017
64
TÃTULO: Cache-aware Roofline Model in Intel® Advisor
AUTORES: Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: ERCIM News, VOLUME: 2017, NÚMERO: 110
AUTORES: Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: ERCIM News, VOLUME: 2017, NÚMERO: 110
INDEXADO EM: 
DBLP
DBLP NO MEU: DBLP
DBLP65
TÃTULO: Performance Analysis with Cache-Aware Roofline Model in Intel Advisor
AUTORES: Diogo Marques; Helder Duarte; Aleksandar Ilic; Leonel Sousa; Roman Belenov; Philippe Thierry; Zakhar A Matveev;
PUBLICAÇÃO: 2017, FONTE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
AUTORES: Diogo Marques; Helder Duarte; Aleksandar Ilic; Leonel Sousa; Roman Belenov; Philippe Thierry; Zakhar A Matveev;
PUBLICAÇÃO: 2017, FONTE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXADO EM: DBLP
DBLP NO MEU: DBLP
DBLP66
TÃTULO: Analyzing Performance of Multi-cores and Applications with Cache-aware Roofline Model
AUTORES: Diogo Marques; Helder Duarte; Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
AUTORES: Diogo Marques; Helder Duarte; Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXADO EM: DBLP
DBLP NO MEU: DBLP
DBLP67
TÃTULO: GPU Parallelization of HEVC In-Loop Filters
AUTORES: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, VOLUME: 45, NÚMERO: 6
AUTORES: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, VOLUME: 45, NÚMERO: 6
INDEXADO EM: 
WOS 
CrossRef
WOS CrossRef68
TÃTULO: Modeling Large Compute Nodes with Heterogeneous Memories with Cache-Aware Roofline Model
AUTORES: Nicolas Denoyelle; Brice Goglin; Aleksandar Ilic; Emmanuel Jeannot; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation - 8th International Workshop, PMBS 2017, Denver, CO, USA, November 13, 2017, Proceedings, VOLUME: 10724
AUTORES: Nicolas Denoyelle; Brice Goglin; Aleksandar Ilic; Emmanuel Jeannot; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation - 8th International Workshop, PMBS 2017, Denver, CO, USA, November 13, 2017, Proceedings, VOLUME: 10724
INDEXADO EM: DBLP
DBLP NO MEU: DBLP
DBLP69
TÃTULO: Cache-aware Roofline Model in Intel (R) Advisor
AUTORES: Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: ERCIM NEWS, NÚMERO: 110
AUTORES: Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: ERCIM NEWS, NÚMERO: 110
INDEXADO EM: WOS
WOS70
TÃTULO: The parameters of Fibonacci and Lucas cubes
AUTORES: Aleksandar Ilic; Marko Milosevic;
PUBLICAÇÃO: 2017, FONTE: Ars Math. Contemp., VOLUME: 12, NÚMERO: 1
AUTORES: Aleksandar Ilic; Marko Milosevic;
PUBLICAÇÃO: 2017, FONTE: Ars Math. Contemp., VOLUME: 12, NÚMERO: 1
INDEXADO EM: DBLP
DBLP NO MEU: DBLP
DBLP