Nuno Filipe Simões Santos Moraes Neves
AuthID: R-00J-05P
11
TÃTULO: HEDAcc: FPGA-based Accelerator for High-order Epistasis Detection
AUTORES: Gaspar Ribeiro; Nuno Neves; Sergio Santander-Jimenez; Aleksandar Ilic;
PUBLICAÇÃO: 2021, FONTE: 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
AUTORES: Gaspar Ribeiro; Nuno Neves; Sergio Santander-Jimenez; Aleksandar Ilic;
PUBLICAÇÃO: 2021, FONTE: 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
12
TÃTULO: Reconfigurable Stream-based Tensor Unit with Variable-Precision Posit Arithmetic
AUTORES: Neves, N; Tomas, P; Roma, N;
PUBLICAÇÃO: 2020, FONTE: 31st IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP) in 2020 IEEE 31ST INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2020), VOLUME: 2020-July
AUTORES: Neves, N; Tomas, P; Roma, N;
PUBLICAÇÃO: 2020, FONTE: 31st IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP) in 2020 IEEE 31ST INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2020), VOLUME: 2020-July
13
TÃTULO: Dynamic Fused Multiply-Accumulate Posit Unit with Variable Exponent Size for Low-Precision DSP Applications
AUTORES: Neves, N; Tomas, P; Roma, N;
PUBLICAÇÃO: 2020, FONTE: 34th IEEE Workshop on Signal Processing Systems, SiPS 2020 in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, VOLUME: 2020-October
AUTORES: Neves, N; Tomas, P; Roma, N;
PUBLICAÇÃO: 2020, FONTE: 34th IEEE Workshop on Signal Processing Systems, SiPS 2020 in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, VOLUME: 2020-October
