Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis

AuthID
 P-003-B9E
2
Author(s)
2
Editor(es)
Monteiro,J;VanLeuken,R
Tipo de Documento
Proceedings Paper
Year published
2010
Publicado
in INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION in Lecture Notes in Computer Science, ISSN: 0302-9743
Volume: 5953, Páginas: 46-55 (10)
Conference
19Th International Workshop on Power and Timing Modeling, Optimization and Simulation, Date: SEP 09-11, 2009, Location: Delft, NETHERLANDS, Patrocinadores: NIRICT Design Lab & Cadence Design Syst & Tech, IEEE, Host: TU Delft
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Publication Identifiers
SCOPUS: 2-s2.0-77951124607
Wos: WOS:000278807700005
Source Identifiers
ISSN: 0302-9743
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