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Improved Clock-Phase Generator Based on Self-Biased Cmos Logic for Time-Interleaved Sc Circuits

AuthID
P-007-T1M

Author(s)

Figueiredo, M

Michalak, T

Goes, J

Gomes, L

Sniatala, P

Tipo de Documento

Proceedings Paper

Year published

2009

Publicado

in 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009

Páginas: 763-766

Conference

2009 16Th Ieee International Conference on Electronics, Circuits and Systems, Icecs 2009, Date: 13 December 2009 through 16 December 2009, Location: Yasmine Hammamet

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Publication Identifiers

DOI: 10.1109/icecs.2009.5410771

SCOPUS: 2-s2.0-77951432156

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Improved Clock-Phase Generator Based on Self-Biased Cmos Logic for Time-Interleaved Sc Circuits

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Improved Clock-Phase Generator Based on Self-Biased Cmos Logic for Time-Interleaved Sc Circuits

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