A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time Σδ Modulators

AuthID
 P-007-YR7
6
Author(s)
Jiang, Y
·
Wong, KF
·
Cai, CY
·
Sin, SW
·
Tipo de Documento
Proceedings Paper
Year published
2010
Publicado
in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Páginas: 1011-1014
Conference
2010 Asia Pacific Conference on Circuit and System, Apccas 2010, Date: 6 December 2010 through 9 December 2010, Location: Kuala Lumpur
Indexing
Scopus®
Crossref®
Google Scholar®
Publication Identifiers
SCOPUS: 2-s2.0-79959207880
Export Publication Metadata
Lista Marked
 Adicionar à lista Marked
Info
At this moment we don't have any links to full text documens.

Um espaço para investigadores e suas Instituições

Links Úteis

Ajuda

© 2024 CRACS & Inesc TEC - All Rights Reserved Política de Privacidade | Terms of Service