Power Optimized Viterbi Decoder Implementation Throught Architectural Transforms

AuthID
 P-000-Y02
2
Author(s)
Portela, J
·
3
Editor(es)
Jacobi, R; Ferrari, A; Carro, L
Tipo de Documento
Proceedings Paper
Year published
2001
Publicado
in 14TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS
Páginas: 212-217 (6)
Conference
14Th Symposium on Integrated Circuits and Systems Design, Date: SEP 10-15, 2001, Location: PIRENOPOLIS, BRAZIL, Patrocinadores: Brazilian Comp Soc, IFIP WG10 5, Brazilian Microelectr Soc, ACM Sigda, Univ Brasilia
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Wos®
Publication Identifiers
Wos: WOS:000171608800034
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