Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates

AuthID
P-00P-4P2
4
Author(s)
Ghissoni, S
·
dos Santos Martins, JBD
·
da Luz Reis, RAD
·
2
Editor(es)
Monteiro, J; VanLeuken, R
Tipo de Documento
Proceedings Paper
Year published
2010
Publicado
in INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION in Lecture Notes in Computer Science, ISSN: 0302-9743
Volume: 5953, Páginas: 297-+ (2)
Conference
19Th International Workshop on Power and Timing Modeling, Optimization and Simulation, Date: SEP 09-11, 2009, Location: TU Delft, Delft, NETHERLANDS, Patrocinadores: NIRICT Design Lab & Cadence Design Syst & Tech, IEEE, Host: TU Delft
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Publication Identifiers
Wos: WOS:000278807700030
Source Identifiers
ISSN: 0302-9743
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