Signal and Power Integrity Io Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages

AuthID
 P-00Y-4Z0
5
Author(s)
Souilem, M
·
Zgolli, N
·
Dghais, W
·
Belgacem, H
Tipo de Documento
Article in Press
Year published
2023
Publicado
in IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, ISSN: 1063-8210
Volume: 31, Número: 6, Páginas: 874-886 (13)
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Publication Identifiers
Wos: WOS:000943487800001
Source Identifiers
ISSN: 1063-8210
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