11
TITLE: Sliding block Viterbi decoders in FPGA
AUTHORS: Vestias, M ; Neto, H ; Sarmento, H ;
PUBLISHED: 2012, SOURCE: 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 in Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
INDEXED IN: Scopus CrossRef
IN MY: ORCID
12
TITLE: Tradeoffs in the design of sliding block Viterbi decoders for MB-OFDM UWB systems
AUTHORS: Vestias, M ; Sarmento, H ;
PUBLISHED: 2012, SOURCE: 2012 IEEE 2nd International Conference on Consumer Electronics - Berlin, ICCE 2012 in IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin
INDEXED IN: Scopus CrossRef
IN MY: ORCID
13
TITLE: A dynamic buffer resize technique for networks-on-chip on FPGA
AUTHORS: Vestias, MP ; Neto, HC ;
PUBLISHED: 2011, SOURCE: 2011 7th Southern Conference on Programmable Logic, SPL 2011 in Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011
INDEXED IN: Scopus CrossRef
IN MY: ORCID
14
TITLE: Iterative decimal multiplication using binary arithmetic
AUTHORS: Vestias, MP ; Neto, HC ;
PUBLISHED: 2011, SOURCE: 2011 7th Southern Conference on Programmable Logic, SPL 2011 in Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011
INDEXED IN: Scopus CrossRef
IN MY: ORCID
15
TITLE: Revisiting the Newton-Raphson iterative method for decimal division
AUTHORS: Vestias, MP ; Neto, HC ;
PUBLISHED: 2011, SOURCE: 21st International Conference on Field Programmable Logic and Applications, FPL 2011 in Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011
INDEXED IN: Scopus CrossRef
IN MY: ORCID
16
TITLE: A DCM Demapper for MB-OFDM on FPGA
AUTHORS: Mario Vestias ; Hugo Santos; Helena Sarmento ;
PUBLISHED: 2010, SOURCE: IEEE International Conference on Consumer Electronics in 2010 DIGEST OF TECHNICAL PAPERS INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS ICCE
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
17
TITLE: Parallel decimal multipliers using binary multipliers
AUTHORS: Vestias, MP ; Neto, HC ;
PUBLISHED: 2010, SOURCE: 6th Southern Programmable Logic Conference, SPL 2010 in 6th Southern Programmable Logic Conference, SPL 2010 - Proceedings
INDEXED IN: Scopus CrossRef
IN MY: ORCID
18
TITLE: Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs
AUTHORS: Rui Duarte; Horacio Neto ; Mario Vestias ;
PUBLISHED: 2009, SOURCE: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools in PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
19
TITLE: Run-Time Reconfigurable Array using Magnetic RAM
AUTHORS: Victor Silva; Luis B Oliveira ; Jorge R Fernandes ; Mario P Vestias ; Horacio C Neto ;
PUBLISHED: 2009, SOURCE: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools in PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
20
TITLE: Architectural tradeoffs in the design of barrel shifters for reconfigurable computing
AUTHORS: Horacio C Neto ; Mario P Vestias ;
PUBLISHED: 2008, SOURCE: 4th Southern Conference on Programmable Logic in 2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
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