Nuno Calado Correia Lourenço


AuthID: R-001-GD2

Confirmed Publications: 79



1
TITLE: Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement
AUTHORS: Ricardo Povoa; Nuno Lourenco ; Ricardo Martins ; Antonio Canelas; Nuno Cavaco G Gomes Horta ; Joao Goes;
PUBLISHED: 2018, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 65, ISSUE: 3
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
2
TITLE: Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving
AUTHORS: Povoa, R; Lourenco, N ; Martins, R ; Canelas, A; Horta, N ; Goes, J;
PUBLISHED: 2018, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 65, ISSUE: 11
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
3
TITLE: A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits
AUTHORS: Póvoa, R; Canelas, A; Martins, R; Lourenço, N ; Horta, N ; Goes, J;
PUBLISHED: 2017, SOURCE: 13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017 in PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings
INDEXED IN: Scopus CrossRef
IN MY: ORCID
4
TITLE: Automatic technology migration of analog IC designs using generic cell libraries
AUTHORS: Jose Cachaco; Nuno Machado; Nuno Lourenço ; Jorge Guilherme; Nuno Horta ;
PUBLISHED: 2017, SOURCE: 20th Design, Automation and Test in Europe, DATE 2017 in Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017
INDEXED IN: Scopus DBLP CrossRef
IN MY: ORCID
5
TITLE: Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing
AUTHORS: Canelas, A; Martins, R; Povoa, R; Lourenco, N ; Horta, N ;
PUBLISHED: 2017, SOURCE: 20th Design, Automation and Test in Europe, DATE 2017 in Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
INDEXED IN: Scopus CrossRef: 2
IN MY: ORCID
6
TITLE: Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks
AUTHORS: Martins, R; Lourenco, N ; Povoa, R; Canelas, A; Horta, N ; Passos, F; Castro Lopez, R; Roca, E; Fernandez, F;
PUBLISHED: 2017, SOURCE: 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 in SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
INDEXED IN: Scopus CrossRef
IN MY: ORCID
7
TITLE: New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization
AUTHORS: Lourenco, N ; Martins, R; Povoa, R; Canelas, A; Horta, N ; Passos, F; Castro Lopez, R; Roca, E; Fernandez, FV;
PUBLISHED: 2017, SOURCE: 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 in SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
INDEXED IN: Scopus CrossRef
IN MY: ORCID
8
TITLE: Stochastic-based placement template generator for analog IC layout-aware synthesis
AUTHORS: Martins, R; Lourenço, N ; Canelas, A; Horta, N ;
PUBLISHED: 2017, SOURCE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 58
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
9
TITLE: Systematic design of a voltage controlled oscillator using a layout-aware approach
AUTHORS: Passos, F; Roca, E; Castro Lopez, R; Fernandez, FV; Martins, R; Lourenco, N ; Povoa, R; Canelas, A; Horta, N ;
PUBLISHED: 2017, SOURCE: 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 in SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
INDEXED IN: Scopus CrossRef
IN MY: ORCID
10
TITLE: AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation  Full Text
AUTHORS: Nuno Lourenco ; Ricardo Martins ; Antonio Canelas; Ricardo Povoa; Nuno Horta ;
PUBLISHED: 2016, SOURCE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 55
INDEXED IN: Scopus WOS CrossRef: 16
IN MY: ORCID
Page 1 of 8. Total results: 79.

A place for researchers and their institutions

Useful Links

Get Help

© 2024 CRACS & Inesc TEC - All Rights Reserved Privacy Policy | Terms of Service