José Carlos Alves Pereira Monteiro


AuthID: R-000-85F

Confirmed Publications: 98



81
TITLE: Observability analysis of embedded software for coverage-directed validation
AUTHORS: Costa, JC; Devadas, S; Monteiro, JC ;
PUBLISHED: 2000, SOURCE: IEEE/ACM International Conference on Computer Aided Design (ICCAD-2000) in ICCAD - 2000 : IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
82
TITLE: Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation
AUTHORS: Flores, P ; Costa, J; Neto, H ; Monteiro, J ; Marques Silva, J ;
PUBLISHED: 1999, SOURCE: 12th International Conference on VLSI Design in TWELFTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS
INDEXED IN: Scopus WOS DBLP CrossRef: 30 Unpaywall
IN MY: ORCID | ResearcherID
83
TITLE: Finite state machine decomposition for low power  Full Text
AUTHORS: Monteiro, JC ; Oliveira, AL ;
PUBLISHED: 1998, SOURCE: 35th Design Automation Conference in 1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | ResearcherID
84
TITLE: Power estimation under user-specified input sequences and programs  Full Text
AUTHORS: Monteiro, J ; Devadas, S;
PUBLISHED: 1998, SOURCE: INTEGRATED COMPUTER-AIDED ENGINEERING, VOLUME: 5, ISSUE: 2
INDEXED IN: Scopus WOS
IN MY: ORCID | ResearcherID
85
TITLE: Power optimization of combinational modules using self-timed precomputation
AUTHORS: Mota, A; Monteiro, J ; Oliveira, A ;
PUBLISHED: 1998, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS 98) in ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, VOLUME: 2
INDEXED IN: Scopus WOS
IN MY: ORCID | ResearcherID
86
TITLE: Sequential logic optimization for low power using input-disabling precomputation architectures  Full Text
AUTHORS: Monteiro, J ; Devadas, S; Ghosh, A;
PUBLISHED: 1998, SOURCE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 17, ISSUE: 3
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID
87
TITLE: Estimation of average switching activity in combinational logic circuits using symbolic simulation  Full Text
AUTHORS: Monteiro, J ; Devadas, S; Ghosh, A; Keutzer, K; White, J;
PUBLISHED: 1997, SOURCE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 16, ISSUE: 1
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID
88
TITLE: Switching activity estimation using limited depth reconvergent path analysis
AUTHORS: Costa, JC; Monteiro, JC ; Devadas, S;
PUBLISHED: 1997, SOURCE: 1997 International Symposium on Low Power Electronics and Design in 1997 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID | ResearcherID
89
TITLE: Power estimation methods for sequential logic circuits (vol 3, pg 404, 1995)  Full Text
AUTHORS: Tsui, CY; Monteiro, J ; Pedram, M; Devadas, S; Despain, AM; Lin, B;
PUBLISHED: 1996, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 4, ISSUE: 4
INDEXED IN: WOS
IN MY: ResearcherID
90
TITLE: Scheduling techniques to enable power management  Full Text
AUTHORS: Monteiro, J ; Devadas, S; Ashar, P; Mauskar, A;
PUBLISHED: 1996, SOURCE: 33rd Design Automation Conference in 33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID
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