Maria J. Avedillo
AuthID: R-006-MCZ
1
TITLE: Improved Nanopipelined RTD Adder Using Generalized Threshold Gates
AUTHORS: Hector Pettenghi ; Maria J Avedillo; Jose M Quintana;
PUBLISHED: 2011, SOURCE: IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOLUME: 10, ISSUE: 1
AUTHORS: Hector Pettenghi ; Maria J Avedillo; Jose M Quintana;
PUBLISHED: 2011, SOURCE: IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOLUME: 10, ISSUE: 1
2
TITLE: An improved RNS generator 2(n) +/- k based on threshold logic
AUTHORS: Hector Pettenghi ; Ricardo Chaves ; Leonel Sousa ; Maria J Avedillo;
PUBLISHED: 2010, SOURCE: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip in PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP
AUTHORS: Hector Pettenghi ; Ricardo Chaves ; Leonel Sousa ; Maria J Avedillo;
PUBLISHED: 2010, SOURCE: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip in PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP
3
TITLE: Non return mobile logic family
AUTHORS: Pettenghi, H; Avedillo, MJ; Quintana, JM;
PUBLISHED: 2007, SOURCE: 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 in Proceedings - IEEE International Symposium on Circuits and Systems
AUTHORS: Pettenghi, H; Avedillo, MJ; Quintana, JM;
PUBLISHED: 2007, SOURCE: 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 in Proceedings - IEEE International Symposium on Circuits and Systems
INDEXED IN: 
Scopus
Scopus4
TITLE: Useful logic blocks based on clocked series-connected RTDs
AUTHORS: Pettenghi, H; Avedillo, MJ; Quintana, JM;
PUBLISHED: 2004, SOURCE: 2004 4th IEEE Conference on Nanotechnology in 2004 4th IEEE Conference on Nanotechnology
AUTHORS: Pettenghi, H; Avedillo, MJ; Quintana, JM;
PUBLISHED: 2004, SOURCE: 2004 4th IEEE Conference on Nanotechnology in 2004 4th IEEE Conference on Nanotechnology
INDEXED IN: Scopus
Scopus