José Carlos Alves Pereira Monteiro
AuthID: R-000-85F
41
TITLE: Optimization of combinational and sequential logic circuits for low power using precomputation
AUTHORS: Monteiro, J; Rinderknecht, J; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings Sixteenth Conference on Advanced Research in VLSI
AUTHORS: Monteiro, J; Rinderknecht, J; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings Sixteenth Conference on Advanced Research in VLSI
42
TITLE: Retiming sequential circuits for low power
AUTHORS: Monteiro, J; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
AUTHORS: Monteiro, J; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
43
TITLE: Probabilistic bottom-up RTL power estimation
AUTHORS: Ferreira, R; A.-M Trullemans; Costa, J; Monteiro, J;
PUBLISHED: 2002, SOURCE: Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)
AUTHORS: Ferreira, R; A.-M Trullemans; Costa, J; Monteiro, J;
PUBLISHED: 2002, SOURCE: Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)
44
TITLE: Power efficient arithmetic operand encoding [CMOS circuits]
AUTHORS: Costa, E; Bampi, S; Monteiro, J;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
AUTHORS: Costa, E; Bampi, S; Monteiro, J;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
45
TITLE: Power optimized Viterbi decoder implementation through architectural transforms
AUTHORS: Portela, J; Monteiro, J;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
AUTHORS: Portela, J; Monteiro, J;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
46
TITLE: A probabilistic approach for RT-level power modeling
AUTHORS: Costa, J; Monteiro, J; Silveira, L. Miguel ; Devadas, S;
PUBLISHED: 1999, SOURCE: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, VOLUME: 2
AUTHORS: Costa, J; Monteiro, J; Silveira, L. Miguel ; Devadas, S;
PUBLISHED: 1999, SOURCE: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, VOLUME: 2
47
TITLE: Computer-Aided Design Techniques for Low Power Sequential Logic Circuits
AUTHORS: José Monteiro; Srinivas Devadas;
PUBLISHED: 1997
AUTHORS: José Monteiro; Srinivas Devadas;
PUBLISHED: 1997
48
TITLE: Power estimation methods for sequential logic circuits Full Text
AUTHORS: Chi-Ying Tsui, ; Monteiro, J; Massoud Pedram, ; Srinivas Devadas, ; A.M Despain; Lin, B;
PUBLISHED: 1995, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems - IEEE Trans. VLSI Syst., VOLUME: 3, ISSUE: 3
AUTHORS: Chi-Ying Tsui, ; Monteiro, J; Massoud Pedram, ; Srinivas Devadas, ; A.M Despain; Lin, B;
PUBLISHED: 1995, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems - IEEE Trans. VLSI Syst., VOLUME: 3, ISSUE: 3
