On the Analysis of Routing, Cells and Adjacency Faults in Cmos Digital Circuits

AuthID
P-007-6DX
4
Author(s)
Casimiro, AP
·
1
Editor(s)
Anon
Document Type
Proceedings Paper
Year published
1994
Published
in IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, ISSN: 1063-6722
Pages: 263-270
Conference
Proceedings of the 1994 Ieee International Workshop on Defect and Fault Tolerance in Vlsi Systems, Date: 17 October 1994 through 19 October 1994, Location: Montreal, Que, Can, Sponsors: IEEE
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Publication Identifiers
SCOPUS: 2-s2.0-0028747906
Source Identifiers
ISSN: 1063-6722
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