Mário Pereira Véstias


AuthID: R-000-CZ3

Publicações Confirmadas: 29



21
TÍTULO: DECIMAL MULTIPLIER ON FPGA USING EMBEDDED BINARY MULTIPLIERS
AUTORES: Horacio C Neto ; Mario R Vestias ;
PUBLICAÇÃO: 2008, FONTE: 18th International Conference on Field Programmable and Logic Applications in 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2
INDEXADO EM: Scopus WOS CrossRef
NO MEU: ORCID
22
TÍTULO: Multiplier-based double precision floating point divider according to the IEEE-754 standard  Full Text
AUTORES: Vitor Silva; Rui Duarte; Mario Vestias ; Horacio Neto ;
PUBLICAÇÃO: 2008, FONTE: 4th International Workshop on Applied Reconfigurable Computing in RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, VOLUME: 4943
INDEXADO EM: Scopus WOS CrossRef
NO MEU: ORCID
23
TÍTULO: Router design for application specific networks-on-chip on reconfigurable systems
AUTORES: Mario P Vestias ; Horacio C Neto ;
PUBLICAÇÃO: 2007, FONTE: 17th International Conference on Field Programmable Logic and Applications in 2007 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLS 1 AND 2
INDEXADO EM: Scopus WOS CrossRef
NO MEU: ORCID
24
TÍTULO: A generic network-on-chip architecture for reconfigurable systems: Implementation and evaluation
AUTORES: Vestias, MP ; Neto, HC ;
PUBLICAÇÃO: 2006, FONTE: 2006 International Conference on Field Programmable Logic and Applications, FPL in Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
INDEXADO EM: Scopus CrossRef
NO MEU: ORCID
25
TÍTULO: Area and performance optimization of a generic network-on-chip architecture
AUTORES: Vestias, MP ; Neto, HC ;
PUBLICAÇÃO: 2006, FONTE: SBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design in SBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design, VOLUME: 2006
INDEXADO EM: Scopus
NO MEU: ORCID
26
TÍTULO: Area/performance improvement of NoC architectures
AUTORES: Vestias, MP ; Neto, HC ;
PUBLICAÇÃO: 2006, FONTE: 2nd International Workshop on Applied Reconfigurable Computing, ARC 2006 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 3985 LNCS
INDEXADO EM: Scopus
NO MEU: ORCID
27
TÍTULO: Co-synthesis of a configurable SoC platform based on a network on chip architecture
AUTORES: Mario P Vestias ; Horacio C Neto ;
PUBLICAÇÃO: 2006, FONTE: 11th Asia and South Pacific Design Automation Conference in ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, VOLUME: 2006
INDEXADO EM: Scopus WOS CrossRef
NO MEU: ORCID
28
TÍTULO: DALI: A methodology for the co-design of dataflow applications on hardware/software architectures
AUTORES: Vestias, MP ; Neto, HC;
PUBLICAÇÃO: 2003, FONTE: 16th Symposium on Integrated Circuits and Systems Design in 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS
INDEXADO EM: WOS
NO MEU: ORCID
29
TÍTULO: System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures  Full Text
AUTORES: Vestias, MP ; Neto, HC;
PUBLICAÇÃO: 2002, FONTE: 13th IEEE International Workshop on Rapid System Prototyping in 13TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS, VOLUME: 2002-January
INDEXADO EM: Scopus WOS CrossRef
NO MEU: ORCID
Página 3 de 3. Total de resultados: 29.

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