81
TÍTULO: Support for partial run-time reconfiguration of platform FPGAs  Full Text
AUTORES: Miguel L Silva; Joao Canas Ferreira ;
PUBLICAÇÃO: 2006, FONTE: JOURNAL OF SYSTEMS ARCHITECTURE, VOLUME: 52, NÚMERO: 12
INDEXADO EM: Scopus WOS DBLP CrossRef: 20
82
TÍTULO: Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer
AUTORES: João Canas Ferreira ; Miguel M Silva;
PUBLICAÇÃO: 2005, FONTE: 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 in 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, VOLUME: 2005
INDEXADO EM: Scopus DBLP CrossRef: 4
83
TÍTULO: Using a tightly-coupled pipeline in dynamically reconfigurable platform FPGAs
AUTORES: Silva, ML; Ferreira, JC ;
PUBLICAÇÃO: 2005, FONTE: 8th Euromicro Conference on Digital System Design in DSD 2005: 8th Euromicro Conference on Digital System Design, Proceedings, VOLUME: 2005
INDEXADO EM: Scopus WOS DBLP CrossRef
84
TÍTULO: A development support system for applications that use dynamically reconfigurable hardware
AUTORES: Ferreira, JC ; Matos, JS ;
PUBLICAÇÃO: 2004, FONTE: 14th International Conference on Field-Programmable Logic and Applications in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 3203
INDEXADO EM: Scopus WOS DBLP
85
TÍTULO: FAFNER-Accelerating Nesting Problems with FPGAs
AUTORES: José Carlos Alves ; João Canas Ferreira ; Albuquerque, C; José Fernando Oliveira ; José Soeiro Ferreira ; José Silva Matos;
PUBLICAÇÃO: 1999, FONTE: Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCMM 1999) in 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA
INDEXADO EM: Scopus DBLP CrossRef
NO MEU: ORCID | DBLP
86
TÍTULO: A prototype system for rapid application development using dynamically reconfigurable hardware
AUTORES: Ferreira, JC ; Matos, JS ;
PUBLICAÇÃO: 1998, FONTE: IEEE Symposium on FPGAs for Custom Computing Machines in IEEE SYMPOSIUM ON FPGAS FOR CUSTOM COMPUTING MACHINES, PROCEEDINGS
INDEXADO EM: WOS DBLP CrossRef
87
TÍTULO: Flexible hardware acceleration for nesting problems
AUTORES: João Canas Ferreira ; José Carlos Alves ; Albuquerque, C; José Fernando Oliveira ; José Soeiro Ferreira ; José Silva Matos;
PUBLICAÇÃO: 1998, FONTE: Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology in 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998 , VOLUME: 1
INDEXADO EM: Scopus DBLP CrossRef: 1
NO MEU: ORCID | DBLP
88
TÍTULO: Mixed hardware/software applications on dynamically reconfigurable hardware
AUTORES: João Canas Ferreira ; José Silva Matos;
PUBLICAÇÃO: 1998, FONTE: Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology in 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998 , VOLUME: 1
INDEXADO EM: Scopus DBLP CrossRef
NO MEU: ORCID | DBLP
89
TÍTULO: An Approach to Testability Improvement of Mixed-Signal Boards
AUTORES: José Silva Matos; João Canas Ferreira ; Ana C Leão; José Machado da Silva;
PUBLICAÇÃO: 1994, FONTE: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994
INDEXADO EM: DBLP
NO MEU: ORCID | DBLP
90
TÍTULO: AN APPROACH TO TESTABILITY IMPROVEMENT OF MIXED-SIGNAL BOARDS
AUTORES: MATOS, JS; FERREIRA, JC ; LEAO, AC;
PUBLICAÇÃO: 1994, FONTE: 1994 IEEE International Symposium on Circuits and Systems in 1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 6: NONLINEAR CIRCUITS AND SYSTEMS (NCS) - NEURAL SYSTEMS (NEU)
INDEXADO EM: WOS
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