61
TÍTULO: Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations  Full Text
AUTORES: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLICAÇÃO: 2014, FONTE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, NÚMERO: 2
INDEXADO EM: Scopus CrossRef: 15
NO MEU: ORCID
62
TÍTULO: SchedMon: A Performance and Energy Monitoring Tool for Modern Multi-cores
AUTORES: Luis Tanica; Aleksandar Ilic; Pedro Tomas ; Leonel Sousa ;
PUBLICAÇÃO: 2014, FONTE: 20th Euro-Par International Workshops in EURO-PAR 2014: PARALLEL PROCESSING WORKSHOPS, PT II, VOLUME: 8806
INDEXADO EM: Scopus WOS DBLP CrossRef: 7
NO MEU: ORCID | DBLP
63
TÍTULO: Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs  Full Text
AUTORES: Tiago Dias; Nuno Roma ; Leonel Sousa ;
PUBLICAÇÃO: 2014, FONTE: EURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSING, VOLUME: 2014, NÚMERO: 1
INDEXADO EM: Scopus WOS DBLP CrossRef
NO MEU: ORCID | DBLP
64
TÍTULO: A Compact and Scalable RNS Architecture  Full Text
AUTORES: Pedro Miguens Matutino; Ricardo Chaves ; Leonel Sousa ;
PUBLICAÇÃO: 2013, FONTE: IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) in PROCEEDINGS OF THE 2013 IEEE 24TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 13)
INDEXADO EM: Scopus WOS DBLP CrossRef
NO MEU: ORCID | DBLP
65
TÍTULO: A comparison of computing architectures and parallelization frameworks based on a two-dimensional FDTD
AUTORES: Kuan, L; Tomas, P ; Sousa, L ;
PUBLICAÇÃO: 2013, FONTE: 2013 11th International Conference on High Performance Computing and Simulation, HPCS 2013 in Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013
INDEXADO EM: Scopus DBLP CrossRef: 2
NO MEU: ORCID | DBLP
66
TÍTULO: A Lab Project on the Design and Implementation of Programmable and Configurable Embedded Systems  Full Text
AUTORES: Leonel Sousa ; Samuel Antao; Jose Germano ;
PUBLICAÇÃO: 2013, FONTE: IEEE TRANSACTIONS ON EDUCATION, VOLUME: 56, NÚMERO: 3
INDEXADO EM: Scopus WOS DBLP CrossRef
67
TÍTULO: Accelerating the Computation of Induced Dipoles for Molecular Mechanics with Dataflow Engines
AUTORES: Frederico Pratas; Diego Oriato; Oliver Pell; Ricardo A Mata; Leonel Sousa ;
PUBLICAÇÃO: 2013, FONTE: 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) in 2013 IEEE 21ST ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM)
INDEXADO EM: Scopus WOS DBLP CrossRef
NO MEU: ORCID | DBLP
68
TÍTULO: AN RNS-BASED ARCHITECTURE TARGETING HARDWARE ACCELERATORS FOR MODULAR ARITHMETIC
AUTORES: Samuel Antao; Leonel Sousa ;
PUBLICAÇÃO: 2013, FONTE: IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) in 2013 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP)
INDEXADO EM: Scopus WOS DBLP CrossRef
NO MEU: ORCID | DBLP
69
TÍTULO: DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks
AUTORES: Ambrose, JA; Pettenghi, H ; Sousa, L ;
PUBLICAÇÃO: 2013, FONTE: 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
INDEXADO EM: Scopus DBLP CrossRef
NO MEU: ORCID | DBLP
70
TÍTULO: High performance multi-standard architecture for DCT computation in H.264/AVC High Profile and HEVC codecs
AUTORES: Dias, T; Roma, N ; Sousa, L ;
PUBLICAÇÃO: 2013, FONTE: 2013 7th Conference on Design and Architectures for Signal and Image Processing, DASIP 2013 in Conference on Design and Architectures for Signal and Image Processing, DASIP
INDEXADO EM: Scopus DBLP
NO MEU: ORCID | DBLP
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