Mário Pereira Véstias
AuthID: R-000-CZ3
61
TÃTULO: Parallel Dot-Products for Deep Learning on FPGA
AUTORES: Mario Vestias; Rui Policarpo Duarte; Jose T de Sousa; Horacio Neto;
PUBLICAÇÃO: 2017, FONTE: 27th International Conference on Field Programmable Logic and Applications (FPL) in 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
AUTORES: Mario Vestias; Rui Policarpo Duarte; Jose T de Sousa; Horacio Neto;
PUBLICAÇÃO: 2017, FONTE: 27th International Conference on Field Programmable Logic and Applications (FPL) in 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
INDEXADO EM: 
WOS
WOS NO MEU: 
ORCID
ORCID62
TÃTULO: System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing
AUTORES: Jose M P Nascimento; Mario Vestias;
PUBLICAÇÃO: 2016, FONTE: JOURNAL OF APPLIED REMOTE SENSING, VOLUME: 10, NÚMERO: 1
AUTORES: Jose M P Nascimento; Mario Vestias;
PUBLICAÇÃO: 2016, FONTE: JOURNAL OF APPLIED REMOTE SENSING, VOLUME: 10, NÚMERO: 1
63
TÃTULO: Multi-core for K-means clustering on FPGA
AUTORES: Canilho, J; Véstias, M; Neto, H;
PUBLICAÇÃO: 2016, FONTE: 26th International Conference on Field-Programmable Logic and Applications, FPL 2016 in FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications
AUTORES: Canilho, J; Véstias, M; Neto, H;
PUBLICAÇÃO: 2016, FONTE: 26th International Conference on Field-Programmable Logic and Applications, FPL 2016 in FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications
64
TÃTULO: Multi-Core for K-Means Clustering on FPGA
AUTORES: Canilho, J; Vestias, M; Neto, H;
PUBLICAÇÃO: 2016, FONTE: 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
AUTORES: Canilho, J; Vestias, M; Neto, H;
PUBLICAÇÃO: 2016, FONTE: 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
INDEXADO EM: WOS
WOS NO MEU: ORCID
ORCID65
TÃTULO: XtokaxtikoX: A Stochastic Computing-Based Autonomous Cyber-Physical System
AUTORES: Duarte, RP; Neto, H; Vestias, M;
PUBLICAÇÃO: 2016, FONTE: IEEE International Conference on Rebooting Computing (ICRC) in 2016 IEEE INTERNATIONAL CONFERENCE ON REBOOTING COMPUTING (ICRC)
AUTORES: Duarte, RP; Neto, H; Vestias, M;
PUBLICAÇÃO: 2016, FONTE: IEEE International Conference on Rebooting Computing (ICRC) in 2016 IEEE INTERNATIONAL CONFERENCE ON REBOOTING COMPUTING (ICRC)
66
TÃTULO: Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication
AUTORES: Jose, WM; Silva, AR; Vestias, MP; Neto, HC;
PUBLICAÇÃO: 2015, FONTE: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, VOLUME: 82, NÚMERO: 1
AUTORES: Jose, WM; Silva, AR; Vestias, MP; Neto, HC;
PUBLICAÇÃO: 2015, FONTE: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, VOLUME: 82, NÚMERO: 1
INDEXADO EM: 
Scopus WOS
Scopus WOS NO MEU: ORCID
ORCID67
TÃTULO: A Many-Core Co-Processor for Embedded Parallel Computing on FPGA
AUTORES: Wilson Jose; Horacio Neto; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTORES: Wilson Jose; Horacio Neto; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
68
TÃTULO: Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture
AUTORES: Joao Pinhao; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTORES: Joao Pinhao; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
69
TÃTULO: Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA
AUTORES: Tiago Rodrigues; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTORES: Tiago Rodrigues; Mario Vestias;
PUBLICAÇÃO: 2015, FONTE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
70
TÃTULO: FPGA-based Architecture for Hyperspectral Unmixing
AUTORES: Nascimento, JMP; Vestias, M; Martin, G;
PUBLICAÇÃO: 2015, FONTE: IEEE International Geoscience and Remote Sensing Symposium (IGARSS) in 2015 IEEE INTERNATIONAL GEOSCIENCE AND REMOTE SENSING SYMPOSIUM (IGARSS)
AUTORES: Nascimento, JMP; Vestias, M; Martin, G;
PUBLICAÇÃO: 2015, FONTE: IEEE International Geoscience and Remote Sensing Symposium (IGARSS) in 2015 IEEE INTERNATIONAL GEOSCIENCE AND REMOTE SENSING SYMPOSIUM (IGARSS)
INDEXADO EM: WOS
WOS NO MEU: ORCID
ORCID