Andreas Veneris
AuthID: R-00G-7GJ
1
TÃTULO: Automated Design Debugging With Maximum Satisfiability Full Text
AUTORES: Chen, YB; Safarpour, S; Marques Silva, J ; Veneris, A;
PUBLICAÇÃO: 2010, FONTE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 29, NÚMERO: 11
AUTORES: Chen, YB; Safarpour, S; Marques Silva, J ; Veneris, A;
PUBLICAÇÃO: 2010, FONTE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 29, NÚMERO: 11
2
TÃTULO: Spatial and temporal design debug using partial MaxSAT
AUTORES: Yibin Chen; Sean Safarpour; Andreas G Veneris; João P Marques Silva ;
PUBLICAÇÃO: 2009, FONTE: 19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 in Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009
AUTORES: Yibin Chen; Sean Safarpour; Andreas G Veneris; João P Marques Silva ;
PUBLICAÇÃO: 2009, FONTE: 19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 in Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009
