(Shawn) D. Blanton
AuthID: R-00H-46F
1
TÃTULO: IC Protection Against JTAG-Based Attacks Full Text
AUTORES: Xuanle L Ren; Francisco Pimentel Torres; Blanton, RD; Vitor Grade Tavares ;
PUBLICAÇÃO: 2019, FONTE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 38, NÚMERO: 1
AUTORES: Xuanle L Ren; Francisco Pimentel Torres; Blanton, RD; Vitor Grade Tavares ;
PUBLICAÇÃO: 2019, FONTE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 38, NÚMERO: 1
2
TÃTULO: Detection of IJTAG Attacks Using LDPC-based Feature Reduction and Machine Learning
AUTORES: Xuanle L Ren; (Shawn) D S Blanton; Vitor Grade Tavares ;
PUBLICAÇÃO: 2018, FONTE: 23rd IEEE European Test Symposium (ETS) in 2018 23RD IEEE EUROPEAN TEST SYMPOSIUM (ETS), VOLUME: 2018-May
AUTORES: Xuanle L Ren; (Shawn) D S Blanton; Vitor Grade Tavares ;
PUBLICAÇÃO: 2018, FONTE: 23rd IEEE European Test Symposium (ETS) in 2018 23RD IEEE EUROPEAN TEST SYMPOSIUM (ETS), VOLUME: 2018-May
3
TÃTULO: A Learning-based Approach to Secure JTAG against Unseen Scan-based Attacks
AUTORES: Xuanle L Ren ; (Shawn) D Blanton; Vitor Grade Tavares ;
PUBLICAÇÃO: 2016, FONTE: IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI) in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), VOLUME: 2016-September
AUTORES: Xuanle L Ren ; (Shawn) D Blanton; Vitor Grade Tavares ;
PUBLICAÇÃO: 2016, FONTE: IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI) in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), VOLUME: 2016-September
4
TÃTULO: Detection of Illegitimate Access to JTAG via Statistical Learning in Chip
AUTORES: Xuanle L Ren; Vitor Grade Tavares ; (Shawn) D Blanton;
PUBLICAÇÃO: 2015, FONTE: Conference on Design Automation Test in Europe (DATE) in 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), VOLUME: 2015-April
AUTORES: Xuanle L Ren; Vitor Grade Tavares ; (Shawn) D Blanton;
PUBLICAÇÃO: 2015, FONTE: Conference on Design Automation Test in Europe (DATE) in 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), VOLUME: 2015-April
INDEXADO EM: 
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WOS
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TÃTULO: Bayesian Model Fusion: Enabling Test Cost Reduction of Analog/RF Circuits via Wafer-level Spatial Variation Modeling Full Text
AUTORES: Shanghang H Zhang; Xin Li; (Shawn) D Blanton; Jose Machado da Silva ; John M Carulli; Kenneth M Butler;
PUBLICAÇÃO: 2014, FONTE: 45th IEEE International Test Conference (ITC) in 2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC), VOLUME: 2015-February
AUTORES: Shanghang H Zhang; Xin Li; (Shawn) D Blanton; Jose Machado da Silva ; John M Carulli; Kenneth M Butler;
PUBLICAÇÃO: 2014, FONTE: 45th IEEE International Test Conference (ITC) in 2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC), VOLUME: 2015-February
