José Carlos Alves Pereira Monteiro
AuthID: R-000-85F
41
TÃTULO: A comparison of layout implementations of pipelined and non-pipelined signed radix-4 array multiplier and modified booth multiplier architectures
AUTORES: Leonardo L de Oliveira; Cristiano Santos; Daniel Ferrao; Eduardo Costa; Jose Monteiro; Joao Baptista Martins; Sergio Bampi; Ricardo Reis;
PUBLICAÇÃO: 2007, FONTE: 13th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005) in VLSI-SOC: FROM SYSTEMS TO SILICON, VOLUME: 240
AUTORES: Leonardo L de Oliveira; Cristiano Santos; Daniel Ferrao; Eduardo Costa; Jose Monteiro; Joao Baptista Martins; Sergio Bampi; Ricardo Reis;
PUBLICAÇÃO: 2007, FONTE: 13th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005) in VLSI-SOC: FROM SYSTEMS TO SILICON, VOLUME: 240
INDEXADO EM: 
WOS
WOS42
TÃTULO: Gray encoded arithmetic operators applied to FFT and FIR dedicated datapaths
AUTORES: Eduardo A C da Costa; Jose C Monteiro; Sergio Bampi;
PUBLICAÇÃO: 2006, FONTE: 12th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003) in VLSI-SOC: FROM SYSTEMS TO CHIPS, VOLUME: 200
AUTORES: Eduardo A C da Costa; Jose C Monteiro; Sergio Bampi;
PUBLICAÇÃO: 2006, FONTE: 12th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003) in VLSI-SOC: FROM SYSTEMS TO CHIPS, VOLUME: 200
INDEXADO EM: WOS
WOS43
TÃTULO: Precomputation-based Sequential Logic Optimization For Low Power
AUTORES: Alidina, M; Monteiro, J; Devadas, S; Ghosh, A; Papefthymiou, M;
PUBLICAÇÃO: 2005, FONTE: IEEE/ACM International Conference on Computer-Aided Design
AUTORES: Alidina, M; Monteiro, J; Devadas, S; Ghosh, A; Papefthymiou, M;
PUBLICAÇÃO: 2005, FONTE: IEEE/ACM International Conference on Computer-Aided Design
44
TÃTULO: Low Power Architectures for FFT and FIR Dedicated Datapaths
AUTORES: Costa, E; Bampi, S; Monteiro, J;
PUBLICAÇÃO: 2003, FONTE: 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 in Midwest Symposium on Circuits and Systems, VOLUME: 3
AUTORES: Costa, E; Bampi, S; Monteiro, J;
PUBLICAÇÃO: 2003, FONTE: 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 in Midwest Symposium on Circuits and Systems, VOLUME: 3
45
TÃTULO: Optimization of combinational and sequential logic circuits for low power using precomputation
AUTORES: Monteiro, J; Rinderknecht, J; Devadas, S; Ghosh, A;
PUBLICAÇÃO: 2002, FONTE: Proceedings Sixteenth Conference on Advanced Research in VLSI
AUTORES: Monteiro, J; Rinderknecht, J; Devadas, S; Ghosh, A;
PUBLICAÇÃO: 2002, FONTE: Proceedings Sixteenth Conference on Advanced Research in VLSI
46
TÃTULO: Retiming sequential circuits for low power
AUTORES: Monteiro, J; Devadas, S; Ghosh, A;
PUBLICAÇÃO: 2002, FONTE: Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
AUTORES: Monteiro, J; Devadas, S; Ghosh, A;
PUBLICAÇÃO: 2002, FONTE: Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
47
TÃTULO: Probabilistic bottom-up RTL power estimation
AUTORES: Ferreira, R; A.-M Trullemans; Costa, J; Monteiro, J;
PUBLICAÇÃO: 2002, FONTE: Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)
AUTORES: Ferreira, R; A.-M Trullemans; Costa, J; Monteiro, J;
PUBLICAÇÃO: 2002, FONTE: Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)
48
TÃTULO: Power efficient arithmetic operand encoding [CMOS circuits]
AUTORES: Costa, E; Bampi, S; Monteiro, J;
PUBLICAÇÃO: 2001, FONTE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
AUTORES: Costa, E; Bampi, S; Monteiro, J;
PUBLICAÇÃO: 2001, FONTE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
49
TÃTULO: Power optimized Viterbi decoder implementation through architectural transforms
AUTORES: Portela, J; Monteiro, J;
PUBLICAÇÃO: 2001, FONTE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
AUTORES: Portela, J; Monteiro, J;
PUBLICAÇÃO: 2001, FONTE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
50
TÃTULO: A probabilistic approach for RT-level power modeling
AUTORES: Costa, J; Monteiro, J; Silveira, L. Miguel ; Devadas, S;
PUBLICAÇÃO: 1999, FONTE: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, VOLUME: 2
AUTORES: Costa, J; Monteiro, J; Silveira, L. Miguel ; Devadas, S;
PUBLICAÇÃO: 1999, FONTE: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, VOLUME: 2
