Leonel Augusto Pires Seabra Sousa
AuthID: R-000-93B
181
TÃTULO: On Boosting Energy-Efficiency of Heterogeneous Embedded Systems via Game Theory
AUTORES: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
AUTORES: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLICAÇÃO: 2017, FONTE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
183
TÃTULO: Parallel Programming Framework for H.264/AVC Video Encoding in Multicore Systems
AUTORES: Roma, N; Rodrigues, A; Sousa, L;
PUBLICAÇÃO: 2017, FONTE: Programming Multicore and Many-Core Computing Systems
AUTORES: Roma, N; Rodrigues, A; Sousa, L;
PUBLICAÇÃO: 2017, FONTE: Programming Multicore and Many-Core Computing Systems
184
TÃTULO: A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo 2<i><SUP>n</SUP></i>+1 Multiplier
AUTORES: Mirhosseini, SM; Molahosseini, AS; Hosseinzadeh, M; Sousa, L; Martins, P;
PUBLICAÇÃO: 2017, FONTE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 64, NÚMERO: 7
AUTORES: Mirhosseini, SM; Molahosseini, AS; Hosseinzadeh, M; Sousa, L; Martins, P;
PUBLICAÇÃO: 2017, FONTE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 64, NÚMERO: 7
185
TÃTULO: Exploring GPU performance, power and energy-efficiency bounds with Cache-aware Roofline Modeling
AUTORES: Andre Lopes; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: 2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017
AUTORES: Andre Lopes; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: 2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017
186
TÃTULO: Cache-aware Roofline Model in Intel® Advisor
AUTORES: Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: ERCIM News, VOLUME: 2017, NÚMERO: 110
AUTORES: Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: ERCIM News, VOLUME: 2017, NÚMERO: 110
INDEXADO EM: 
DBLP
DBLP NO MEU: DBLP
DBLP187
TÃTULO: Efficient reductions in cyclotomic rings - Application to R-LWE based FHE schemes
AUTORES: Jean Claude Bajard; Julien Eynard; Anwar Hasan; Paulo Martins; Leonel Sousa; Vincent Zucca;
PUBLICAÇÃO: 2017, FONTE: IACR Cryptology ePrint Archive, VOLUME: 2017
AUTORES: Jean Claude Bajard; Julien Eynard; Anwar Hasan; Paulo Martins; Leonel Sousa; Vincent Zucca;
PUBLICAÇÃO: 2017, FONTE: IACR Cryptology ePrint Archive, VOLUME: 2017
INDEXADO EM: DBLP
DBLP NO MEU: DBLP
DBLP188
TÃTULO: A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo 2n + 1 Multiplier
AUTORES: Seyed Mostafa Mirhosseini; Amir Sabbagh Molahosseini; Mehdi Hosseinzadeh; Leonel Sousa; Paulo Martins;
PUBLICAÇÃO: 2017, FONTE: IEEE Trans. on Circuits and Systems, VOLUME: 64, NÚMERO: 7
AUTORES: Seyed Mostafa Mirhosseini; Amir Sabbagh Molahosseini; Mehdi Hosseinzadeh; Leonel Sousa; Paulo Martins;
PUBLICAÇÃO: 2017, FONTE: IEEE Trans. on Circuits and Systems, VOLUME: 64, NÚMERO: 7
INDEXADO EM: DBLP
DBLP NO MEU: DBLP
DBLP189
TÃTULO: Performance Analysis with Cache-Aware Roofline Model in Intel Advisor
AUTORES: Diogo Marques; Helder Duarte; Aleksandar Ilic; Leonel Sousa; Roman Belenov; Philippe Thierry; Zakhar A Matveev;
PUBLICAÇÃO: 2017, FONTE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
AUTORES: Diogo Marques; Helder Duarte; Aleksandar Ilic; Leonel Sousa; Roman Belenov; Philippe Thierry; Zakhar A Matveev;
PUBLICAÇÃO: 2017, FONTE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXADO EM: DBLP
DBLP NO MEU: DBLP
DBLP190
TÃTULO: Analyzing Performance of Multi-cores and Applications with Cache-aware Roofline Model
AUTORES: Diogo Marques; Helder Duarte; Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
AUTORES: Diogo Marques; Helder Duarte; Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXADO EM: DBLP
DBLP NO MEU: DBLP
DBLP