Coarse/Fine-Grained Approaches for Pipelining Computing Stages in Fpga-Based Multicore Architectures

AuthID
P-00A-4JB
2
Author(s)
1
Editor(es)
Lopes, L
Tipo de Documento
Proceedings Paper
Year published
2014
Publicado
in EURO-PAR 2014: PARALLEL PROCESSING WORKSHOPS, PT II in Lecture Notes in Computer Science, ISSN: 0302-9743
Volume: 8806, Páginas: 266-278 (13)
Conference
20Th Euro-Par International Workshops, Date: AUG 25-26, 2014, Location: Porto, PORTUGAL, Patrocinadores: Center for Research in Advanced Computing Systems / INESC-TEC;Computer Science Department / FCUP;Faculty of Sciences, University of Porto;ho-COMPUTER - Compiler & Tools;Microsoft Corporation;Springer International Publishers;UT Austin | Portugal
Indexing
Publication Identifiers
DBLP: conf/europar/AzarianC14
SCOPUS: 2-s2.0-84920080728
Wos: WOS:000354785000023
Source Identifiers
ISSN: 0302-9743
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