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Scheduling Evaluation Tasks for Increased Efficiency of Parallel Analog Ic Synthesis

AuthID
P-00K-16G

Author(s)

Neves, D

Lourenco, N

Horta, N

Tipo de Documento

Proceedings Paper

Year published

2015

Publicado

in 2015 INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD)

Conference

International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (Smacd), Date: SEP 07-07, 2015, Location: Istanbul, TURKEY

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Fontes

Publication Identifiers

DOI: 10.1109/smacd.2015.7301700

SCOPUS: 2-s2.0-84949575523

Wos: WOS:000380412000027

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Scheduling Evaluation Tasks for Increased Efficiency of Parallel Analog Ic Synthesis

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