Publicações

Area-Delay-Power-Aware Adder Placement Method for Rns Reverse Converter Design

AuthID
P-00K-WW2

Author(s)

Zarandi, AAE

Molahosseini, AS

Sousa, L

Hosseinzadeh, M

Navi, K

Editor(es)

Julian, P; Andreou, AG

Tipo de Documento

Proceedings Paper

Year published

2016

Publicado

in 2016 IEEE 7TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS) in IEEE Latin American Symposium on Circuits and Systems, ISSN: 2330-9954

Páginas: 223-226 (4)

Conference

7Th Ieee Latin American Symposium on Circuits and Systems (Lascas), Date: FEB 28-MAR 02, 2016, Location: Florianopolis, BRAZIL, Patrocinadores: IEEE, Univ Fed Santa Catarina, MentorGraphics, Creat Solut, Macnica DHW, Synopsys, imec

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Dblp^®/pt/publications/view/652162

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Metadata
Fontes

Publication Identifiers

DOI: 10.1109/LASCAS.2016.7451050

DBLP: conf/lascas/ZarandiMSHN16

Wos: WOS:000381984000048

Source Identifiers

ISSN: 2330-9954

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Area-Delay-Power-Aware Adder Placement Method for Rns Reverse Converter Design

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