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A 3Rd Order Mash Switched-Capacitor Σδm Using Ultra Incomplete Settling Employing an Area Reduction Technique

AuthID
P-00N-6TC

Author(s)

Fouto, D

Paulino, N

Tipo de Documento

Proceedings Paper

Year published

2017

Publicado

in Proceedings - IEEE International Symposium on Circuits and Systems, ISSN: 0271-4310

Conference

50Th Ieee International Symposium on Circuits and Systems, Iscas 2017, Date: 28 May 2017 through 31 May 2017, Patrocinadores: IEEE;IEEE Circuits and Systems Society (CAS)

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Fontes

Publication Identifiers

DOI: 10.1109/iscas.2017.8050370

SCOPUS: 2-s2.0-85032710568

Source Identifiers

ISSN: 0271-4310

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A 3Rd Order Mash Switched-Capacitor Σδm Using Ultra Incomplete Settling Employing an Area Reduction Technique

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A 3Rd Order Mash Switched-Capacitor Σδm Using Ultra Incomplete Settling Employing an Area Reduction Technique

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