A 1.6-Gs/S 12.2-Mw Seven-/Eight-Way Split Time-Interleaved Sar Adc Achieving 54.2-Db Sndr With Digital Background Timing Mismatch Calibration

AuthID
 P-00R-VG8
5
Author(s)
Guo, MQ
·
Mao, JJ
·
Sin, SW
·
Wei, HG
·
Tipo de Documento
Article
Year published
2020
Publicado
in IEEE JOURNAL OF SOLID-STATE CIRCUITS, ISSN: 0018-9200
Volume: 55, Número: 3, Páginas: 693-705 (13)
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Publication Identifiers
SCOPUS: 2-s2.0-85080915098
Wos: WOS:000519578200016
Source Identifiers
ISSN: 0018-9200
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