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Performance and Area Modeling of Complete Fpga Designs in the Presence of Loop Transformations

AuthID
P-00T-KC6

Author(s)

Shayee, KRS

Park, J

Diniz, PC

Tipo de Documento

Proceedings Paper

Year published

2003

Publicado

in IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings, ISSN: 1082-3409

Volume: 2003-January, Páginas: 296

Conference

11Th Annual Ieee Symposium on Field-Programmable Custom Computing Machines, Fccm 2003, Date: 9 April 2003 through 11 April 2003, Patrocinadores: IEEE Computer Society Technical Committee on Computer Architecture

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Publication Identifiers

DOI: 10.1109/fpga.2003.1227278

SCOPUS: 2-s2.0-84942870302

Source Identifiers

ISSN: 1082-3409

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Performance and Area Modeling of Complete Fpga Designs in the Presence of Loop Transformations

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Performance and Area Modeling of Complete Fpga Designs in the Presence of Loop Transformations

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