Performance and Area Modeling of Complete Fpga Designs in the Presence of Loop Transformations

AuthID
 P-00T-KCW
3
Author(s)
Park, J
·
Shesha Shayee, KR
Tipo de Documento
Article
Year published
2004
Publicado
in IEEE Transactions on Computers, ISSN: 0018-9340
Volume: 53, Número: 11, Páginas: 1420-1435
Indexing
Scopus®
Crossref®17
Google Scholar®
Publication Identifiers
SCOPUS: 2-s2.0-8744301956
Source Identifiers
ISSN: 0018-9340
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