Defect-Oriented Verilog Fault Simulation of Soc Macros Using a Stratified Fault Sampling Technique

AuthID
P-001-6CX
Document Type
Proceedings Paper
Year published
1999
Published
in 17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS in IEEE VLSI Test Symposium, ISSN: 1093-0167
Pages: 326-332 (3)
Conference
17Th Ieee Very Large Scale Intergration Test Symposium, Date: APR 25-29, 1999, Location: DANA POINT, CA, Sponsors: IEEE, Comp Soc, Tech Comm Test Technol
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Publication Identifiers
SCOPUS: 2-s2.0-0032659637
Wos: WOS:000081779300044
Source Identifiers
ISSN: 1093-0167
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