Ricardo Jorge Fernandes Chaves


AuthID: R-000-FCD

Confirmed Publications: 47



1
TITLE: Method for designing two levels RNS reverse converters for large dynamic ranges  Full Text
AUTHORS: Hector Pettenghi; Ricardo Chaves ; Roberto de Matos; Leonel Sousa ;
PUBLISHED: 2016, SOURCE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 55
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID
2
TITLE: Arithmetic-Based Binary-to-RNS Converter Modulo {2(n)+/- k} for jn-Bit Dynamic Range  Full Text
AUTHORS: Matutino, PM; Chaves, R ; Sousa, L ;
PUBLISHED: 2015, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 23, ISSUE: 3
INDEXED IN: Scopus WOS DBLP
3
TITLE: Challenges in Designing Trustworthy Cryptographic Co-Processors
AUTHORS: Ricardo Chaves ; Giorgio Di Natale; Lejla Batina; Shivam Bhasin; Baris Ege; Apostolos Fournaris; Nele Mentens; Stjepan Picek; Francesco Regazzoni; Vladimir Rozic; Nicolas Sklavos; Bohan H Yang;
PUBLISHED: 2015, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXED IN: WOS
4
TITLE: CLEFIA Implementation with Full Key Expansion
AUTHORS: Joao Carlos Bittencourt; Joao Carlos Resende; Wagner Luiz de Oliveira; Ricardo Chaves ;
PUBLISHED: 2015, SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
5
TITLE: Compact Dual Block AES core on FPGA for CCM Protocol
AUTHORS: Joao Carlos Resende; Ricardo Chaves ;
PUBLISHED: 2015, SOURCE: 25th International Conference on Field Programmable Logic and Applications in 2015 25TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
INDEXED IN: WOS CrossRef
IN MY: ORCID
6
TITLE: Morphable hundred-core heterogeneous architecture for energy-aware computation  Full Text
AUTHORS: Nuno Neves ; Henrique Mendes; Ricardo Jorge Chaves ; Pedro Tomas ; Nuno Roma ;
PUBLISHED: 2015, SOURCE: IET COMPUTERS AND DIGITAL TECHNIQUES, VOLUME: 9, ISSUE: 1
INDEXED IN: Scopus WOS CrossRef: 3
IN MY: ORCID
7
TITLE: An Efficient Scalable RNS Architecture for Large Dynamic Ranges  Full Text
AUTHORS: Pedro Miguens Matutino; Ricardo Chaves ; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, VOLUME: 77, ISSUE: 1-2
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID
8
TITLE: Arithmetic-Based Binary-to-RNS Converter Modulo {2n ±k} for jn-Bit Dynamic Range  Full Text
AUTHORS: Matutino, PM; Chaves, R ; Sousa, L ;
PUBLISHED: 2014, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 3
INDEXED IN: Scopus CrossRef: 8
IN MY: ORCID
9
TITLE: Method for designing Multi-Channel RNS Architectures to prevent Power Analysis SCA
AUTHORS: Hector Pettenghi; Jude Angelo Ambrose; Ricardo Chaves ; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID
10
TITLE: ROM-less RNS-to-binary converter moduli {22n - 1, 22n + 1, 2n - 3, 2n + 3}
AUTHORS: Pedro Miguens Matutino; Ricardo Chaves ; Leonel Sousa;
PUBLISHED: 2014, SOURCE: 14th International Symposium on Integrated Circuits, ISIC 2014 in 2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014
INDEXED IN: Scopus DBLP CrossRef
IN MY: ORCID
Page 1 of 5. Total results: 47.

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