Azadeh Alsadat E. Emrani Zarandi
AuthID: R-007-0KQ
1
TITLE: Low-Precision Floating-Point Formats: From General-Purpose to Application-Specific
AUTHORS: Amir Sabbagh Molahosseini; Leonel Sousa; Azadeh Alsadat Emrani Zarandi; Hans Vandierendonck;
PUBLISHED: 2022, SOURCE: Approximate Computing
AUTHORS: Amir Sabbagh Molahosseini; Leonel Sousa; Azadeh Alsadat Emrani Zarandi; Hans Vandierendonck;
PUBLISHED: 2022, SOURCE: Approximate Computing
INDEXED IN: 
DBLP
DBLP2
TITLE: Low-Precision Floating-Point Formats: From General-Purpose to Application-Specific
AUTHORS: Molahosseini, AS; Sousa, L; Emrani Zarandi, AA; Vandierendonck, H;
PUBLISHED: 2022, SOURCE: Approximate Computing
AUTHORS: Molahosseini, AS; Sousa, L; Emrani Zarandi, AA; Vandierendonck, H;
PUBLISHED: 2022, SOURCE: Approximate Computing
INDEXED IN: 
Scopus
Scopus3
TITLE: Towards Efficient Modular Adders based on Reversible Circuits
AUTHORS: Amir Sabbagh Molahosseini; Ailin Asadpoor; Azadeh Alsadat Emrani Zarandi; Leonel Sousa;
PUBLISHED: 2018, SOURCE: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy
AUTHORS: Amir Sabbagh Molahosseini; Ailin Asadpoor; Azadeh Alsadat Emrani Zarandi; Leonel Sousa;
PUBLISHED: 2018, SOURCE: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy
INDEXED IN: DBLP
DBLP4
TITLE: Area-delay-power-aware adder placement method for RNS reverse converter design
AUTHORS: Zarandi, AAE; Molahosseini, AS; Sousa, L; Hosseinzadeh, M; Navi, K;
PUBLISHED: 2016, SOURCE: 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 in LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
AUTHORS: Zarandi, AAE; Molahosseini, AS; Sousa, L; Hosseinzadeh, M; Navi, K;
PUBLISHED: 2016, SOURCE: 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 in LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
INDEXED IN: Scopus
Scopus5
TITLE: Area-delay-power-aware adder placement method for RNS reverse converter design
AUTHORS: Zarandi, AAE; Molahosseini, AS; Sousa, L; Hosseinzadeh, M; Navi, K;
PUBLISHED: 2016, SOURCE: 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 in LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
AUTHORS: Zarandi, AAE; Molahosseini, AS; Sousa, L; Hosseinzadeh, M; Navi, K;
PUBLISHED: 2016, SOURCE: 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 in LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
INDEXED IN: Scopus
Scopus6
TITLE: Area-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter Design
AUTHORS: Azadeh Alsadat Emrani Zarandi; Amir Sabbagh Molahosseini; Leonel Sousa ; Mehdi Hosseinzadeh; Keivan Navi;
PUBLISHED: 2016, SOURCE: 7th IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2016 IEEE 7TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS)
AUTHORS: Azadeh Alsadat Emrani Zarandi; Amir Sabbagh Molahosseini; Leonel Sousa ; Mehdi Hosseinzadeh; Keivan Navi;
PUBLISHED: 2016, SOURCE: 7th IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2016 IEEE 7TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS)
7
TITLE: Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations Full Text
AUTHORS: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLISHED: 2015, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 23, ISSUE: 2
AUTHORS: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLISHED: 2015, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 23, ISSUE: 2
INDEXED IN: Scopus 
WOS DBLP
Scopus WOS DBLP8
TITLE: Reverse converter design via parallel-prefix adders: Novel components, methodology, and implementations
AUTHORS: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L;
PUBLISHED: 2015, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 2
AUTHORS: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L;
PUBLISHED: 2015, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 2
INDEXED IN: Scopus
Scopus9
TITLE: Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations Full Text
AUTHORS: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLISHED: 2014, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 2
AUTHORS: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLISHED: 2014, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 2
