1
TITLE: A fast SAT Solver strategy based on negated clauses
AUTHORS: Romanelli Zuim; Jose T Sousa; Claudionor N Coelho;
PUBLISHED: 2006, SOURCE: International Conference on Very Large Scale Integration and System-on-Chip in IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP
INDEXED IN: WOS
2
TITLE: LAYOUT-LEVEL TECHNIQUES FOR TESTABILITY IMPROVEMENT OF MOS PHYSICAL DESIGNS
AUTHORS: SANTOS, MB; GONCALVES, FM; SOUSA, JJT; TEIXEIRA, JP;
PUBLISHED: 1991, SOURCE: 6TH MEDITERRANEAN ELECTROTECHNICAL CONF ( MELECON 91 ) in 6TH MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, PROCEEDINGS VOLS 1 AND 2
INDEXED IN: WOS
3
TITLE: High-quality physical designs of CMOS ICs
AUTHORS: Sousa, JJT; Goncalves, FM; Teixeira, JP;
PUBLISHED: 1991, SOURCE: Euro ASIC 1991 in Euro ASIC 1991
INDEXED IN: Scopus