João Paulo de Castro Canas Ferreira


AuthID: R-000-7A5

Publicações Confirmadas: 96



71
TÍTULO: REFLECT: Rendering FPGAs to Multi-core Embedded Computing  Full Text
AUTORES: João M P Cardoso ; Pedro C Diniz; Zlatko Petrov; Koen Bertels; Michael Hübner; Hans van Someren; Fernando Gonçalves; José Gabriel F de Coutinho; George A Constantinides; Bryan Olivier; Wayne Luk; Juergen Becker; Georgi Kuzmanov; Florian Thoma; Lars Braun; Matthias Kühnle; Razvan Nane; Vlad Mihai Sima; Kamil Krátký; José Carlos Alves ; João Canas Ferreira ; ...Mais
PUBLICAÇÃO: 2011, FONTE: Reconfigurable Computing
INDEXADO EM: CrossRef: 14 Handle
NO MEU: ORCID
72
TÍTULO: Creation of Partial FPGA Configurations at Run-Time
AUTORES: Miguel L Silva; Joao Canas Ferreira ;
PUBLICAÇÃO: 2010, FONTE: 13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools in 13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS
INDEXADO EM: Scopus WOS DBLP CrossRef: 4
NO MEU: ORCID | ResearcherID | DBLP
73
TÍTULO: Erlang Inspired Hardware
AUTORES: Paulo Ferreira ; João Canas Ferreira ; José Carlos Alves ;
PUBLICAÇÃO: 2010, FONTE: 20th International Conference on Field Programmable Logic and Applications, FPL 2010 in International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy
INDEXADO EM: Scopus DBLP CrossRef
NO MEU: ORCID | ResearcherID | DBLP
74
TÍTULO: FPGA-based real-time disparity computation and object location
AUTORES: Santos, PM ; Ferreira, JC ;
PUBLICAÇÃO: 2010, FONTE: 28th Norchip Conference, NORCHIP 2010 in 28th Norchip Conference, NORCHIP 2010
INDEXADO EM: Scopus CrossRef: 3
NO MEU: ORCID | ResearcherID
75
TÍTULO: FPGA-based rectification of stereo images
AUTORES: João G P Rodrigues; João Canas Ferreira ;
PUBLICAÇÃO: 2010, FONTE: 2010 Conference on Design and Architectures for Signal and Image Processing, DASIP2010 in Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, DASIP 2010, Edinburgh, Scotland, UK, October 26-28, 2010, Electronic Chips & Systems design Initiative, ECSI
INDEXADO EM: Scopus DBLP CrossRef: 7
NO MEU: ORCID | DBLP
76
TÍTULO: Run-time Generation of Partial Configurations for Arithmetic Expressions  Full Text
AUTORES: Miguel L Silva; Joao Canas Ferreira ;
PUBLICAÇÃO: 2010, FONTE: 53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010) in 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS
INDEXADO EM: Scopus WOS CrossRef
NO MEU: ORCID | ResearcherID
77
TÍTULO: Non-Rectangular Reconfigurable Cores for System-on-Chip
AUTORES: Pedro Alves; Joao Canas Ferreira ;
PUBLICAÇÃO: 2009, FONTE: Conference on VLSI Circuits and Systems IV in VLSI CIRCUITS AND SYSTEMS IV, VOLUME: 7363
INDEXADO EM: Scopus WOS CrossRef
NO MEU: ORCID | ResearcherID
78
TÍTULO: GENERATION OF PARTIAL FPGA CONFIGURATIONS AT RUN-TIME
AUTORES: Miguel L Silva; Joao Canas Ferreira ;
PUBLICAÇÃO: 2008, FONTE: International Conference on Field Programmable and Logic Applications in 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2
INDEXADO EM: Scopus WOS DBLP CrossRef: 15
NO MEU: ORCID | ResearcherID | DBLP
79
TÍTULO: Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems  Full Text
AUTORES: Silva, ML; Ferreira, JC ;
PUBLICAÇÃO: 2007, FONTE: 20th International Conference on Design of Ciruits and Integrated Systems in IET COMPUTERS AND DIGITAL TECHNIQUES, VOLUME: 1, NÚMERO: 5
INDEXADO EM: Scopus WOS DBLP CrossRef: 7
NO MEU: ORCID | ResearcherID | DBLP
80
TÍTULO: Exploiting dynamic reconfiguration of platform FPGAs: implementation issues
AUTORES: Silva, ML; João Canas Ferreira ;
PUBLICAÇÃO: 2006, FONTE: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, VOLUME: 2006
INDEXADO EM: Scopus DBLP CrossRef: 3
NO MEU: ORCID | ResearcherID | DBLP
Página 8 de 10. Total de resultados: 96.

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