Azadeh Alsadat E. Emrani Zarandi
AuthID: R-007-0KQ
1
TÃTULO: Low-Precision Floating-Point Formats: From General-Purpose to Application-Specific
AUTORES: Amir Sabbagh Molahosseini; Leonel Sousa; Azadeh Alsadat Emrani Zarandi; Hans Vandierendonck;
PUBLICAÇÃO: 2022, FONTE: Approximate Computing
AUTORES: Amir Sabbagh Molahosseini; Leonel Sousa; Azadeh Alsadat Emrani Zarandi; Hans Vandierendonck;
PUBLICAÇÃO: 2022, FONTE: Approximate Computing
INDEXADO EM: 
DBLP
DBLP2
TÃTULO: Low-Precision Floating-Point Formats: From General-Purpose to Application-Specific
AUTORES: Molahosseini, AS; Sousa, L; Emrani Zarandi, AA; Vandierendonck, H;
PUBLICAÇÃO: 2022, FONTE: Approximate Computing
AUTORES: Molahosseini, AS; Sousa, L; Emrani Zarandi, AA; Vandierendonck, H;
PUBLICAÇÃO: 2022, FONTE: Approximate Computing
INDEXADO EM: 
Scopus
Scopus3
TÃTULO: Towards Efficient Modular Adders based on Reversible Circuits
AUTORES: Amir Sabbagh Molahosseini; Ailin Asadpoor; Azadeh Alsadat Emrani Zarandi; Leonel Sousa;
PUBLICAÇÃO: 2018, FONTE: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy
AUTORES: Amir Sabbagh Molahosseini; Ailin Asadpoor; Azadeh Alsadat Emrani Zarandi; Leonel Sousa;
PUBLICAÇÃO: 2018, FONTE: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy
INDEXADO EM: DBLP
DBLP4
TÃTULO: Area-delay-power-aware adder placement method for RNS reverse converter design
AUTORES: Zarandi, AAE; Molahosseini, AS; Sousa, L; Hosseinzadeh, M; Navi, K;
PUBLICAÇÃO: 2016, FONTE: 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 in LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
AUTORES: Zarandi, AAE; Molahosseini, AS; Sousa, L; Hosseinzadeh, M; Navi, K;
PUBLICAÇÃO: 2016, FONTE: 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 in LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
INDEXADO EM: Scopus
Scopus5
TÃTULO: Area-delay-power-aware adder placement method for RNS reverse converter design
AUTORES: Zarandi, AAE; Molahosseini, AS; Sousa, L; Hosseinzadeh, M; Navi, K;
PUBLICAÇÃO: 2016, FONTE: 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 in LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
AUTORES: Zarandi, AAE; Molahosseini, AS; Sousa, L; Hosseinzadeh, M; Navi, K;
PUBLICAÇÃO: 2016, FONTE: 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 in LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
INDEXADO EM: Scopus
Scopus6
TÃTULO: Area-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter Design
AUTORES: Azadeh Alsadat Emrani Zarandi; Amir Sabbagh Molahosseini; Leonel Sousa ; Mehdi Hosseinzadeh; Keivan Navi;
PUBLICAÇÃO: 2016, FONTE: 7th IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2016 IEEE 7TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS)
AUTORES: Azadeh Alsadat Emrani Zarandi; Amir Sabbagh Molahosseini; Leonel Sousa ; Mehdi Hosseinzadeh; Keivan Navi;
PUBLICAÇÃO: 2016, FONTE: 7th IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2016 IEEE 7TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS)
7
TÃTULO: Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations Full Text
AUTORES: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLICAÇÃO: 2015, FONTE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 23, NÚMERO: 2
AUTORES: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLICAÇÃO: 2015, FONTE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 23, NÚMERO: 2
INDEXADO EM: Scopus 
WOS DBLP
Scopus WOS DBLP8
TÃTULO: Reverse converter design via parallel-prefix adders: Novel components, methodology, and implementations
AUTORES: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L;
PUBLICAÇÃO: 2015, FONTE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, NÚMERO: 2
AUTORES: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L;
PUBLICAÇÃO: 2015, FONTE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, NÚMERO: 2
INDEXADO EM: Scopus
Scopus9
TÃTULO: Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations Full Text
AUTORES: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLICAÇÃO: 2014, FONTE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, NÚMERO: 2
AUTORES: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLICAÇÃO: 2014, FONTE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, NÚMERO: 2
