José João Henriques Teixeira de Sousa
AuthID: R-000-8D6
1
TÃTULO: A fast SAT Solver strategy based on negated clauses
AUTORES: Romanelli Zuim; Jose T Sousa; Claudionor N Coelho;
PUBLICAÇÃO: 2006, FONTE: International Conference on Very Large Scale Integration and System-on-Chip in IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP
AUTORES: Romanelli Zuim; Jose T Sousa; Claudionor N Coelho;
PUBLICAÇÃO: 2006, FONTE: International Conference on Very Large Scale Integration and System-on-Chip in IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP
INDEXADO EM: WOS
2
TÃTULO: LAYOUT-LEVEL TECHNIQUES FOR TESTABILITY IMPROVEMENT OF MOS PHYSICAL DESIGNS
AUTORES: SANTOS, MB; GONCALVES, FM; SOUSA, JJT; TEIXEIRA, JP;
PUBLICAÇÃO: 1991, FONTE: 6TH MEDITERRANEAN ELECTROTECHNICAL CONF ( MELECON 91 ) in 6TH MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, PROCEEDINGS VOLS 1 AND 2
AUTORES: SANTOS, MB; GONCALVES, FM; SOUSA, JJT; TEIXEIRA, JP;
PUBLICAÇÃO: 1991, FONTE: 6TH MEDITERRANEAN ELECTROTECHNICAL CONF ( MELECON 91 ) in 6TH MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, PROCEEDINGS VOLS 1 AND 2
INDEXADO EM: WOS
3
TÃTULO: High-quality physical designs of CMOS ICs
AUTORES: Sousa, JJT; Goncalves, FM; Teixeira, JP;
PUBLICAÇÃO: 1991, FONTE: Euro ASIC 1991 in Euro ASIC 1991
AUTORES: Sousa, JJT; Goncalves, FM; Teixeira, JP;
PUBLICAÇÃO: 1991, FONTE: Euro ASIC 1991 in Euro ASIC 1991
INDEXADO EM: Scopus