Randomised Multi-Modulo Residue Number System Architecture for Double-And-Add to Prevent Power Analysis Side Channel Attacks

AuthID
 P-008-E5N
4
Author(s)
Jayasinghe, D
·
Tipo de Documento
Article
Year published
2013
Publicado
in IET CIRCUITS DEVICES & SYSTEMS, ISSN: 1751-858X
Volume: 7, Número: 5, Páginas: 283-293 (11)
Indexing
Wos®
Scopus®
Dblp®/pt/publications/view/276661
Crossref®
Google Scholar®
Publication Identifiers
DBLP: journals/iet-cds/AmbrosePJS13
SCOPUS: 2-s2.0-84884306303
Wos: WOS:000326402900008
Source Identifiers
ISSN: 1751-858X
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