ProfileOfResearchers

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TITLE: Delay modeling for power noise-aware design in Spartan-3A FPGAS
AUTHORS: Freijedo, JF; Valdes, MD; Moure, MJ; Costas, L; Rodriguez Andina, JJ; Jorge Semião ; Vargas, F; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 2010, SOURCE: 6th Southern Programmable Logic Conference, SPL 2010 in 6th Southern Programmable Logic Conference, SPL 2010 - Proceedings

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TITLE: Impact of power supply voltage variations on FPGA-based digital systems performance
AUTHORS: Freijedo, J; Costas, L; Jorge Semião ; Rodriguez Andina, JJ; Moure, MJ; Vargas, F; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 2010, SOURCE: Journal of Low Power Electronics, VOLUME: 6, ISSUE: 2

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TITLE: Investigating the use of BICS to detect resistive- open defects in SRAMs
AUTHORS: Chipana, R; Bolzani, L; Vargas, F; Jorge Semião ; Rodriguez Andina, J; Teixeira, I ; Teixeira, P;
PUBLISHED: 2010, SOURCE: 16th IEEE International On-Line Testing Symposium, IOLTS 2010 in Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010

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TITLE: Predictive error detection by on-line aging monitoring
AUTHORS: Vazquez, JC; Champac, V; Ziesemer, AM; Reis, R; Jorge Semião ; Teixeira, IC ; Santos, MB ; Teixeira, JP ;
PUBLISHED: 2010, SOURCE: 16th IEEE International On-Line Testing Symposium, IOLTS 2010 in Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010

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TITLE: Delay-Fault Tolerance to Power Supply Voltage Disturbances Analysis in Nanometer Technologies Full Text
AUTHORS: Jorge Semião ; Freijedo, J; Rodriguez Andina, J; Vargas, F; Santos, M ; Teixeira, I ; Teixeira, P;
PUBLISHED: 2009, SOURCE: 15th IEEE International On-Line Testing Symposium in 2009 15TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM

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TITLE: Measuring Clock-Signal Modulation Efficiency for Systems-on-Chip in Electromagnetic Interference Environment
AUTHORS: Jorge Semião ; Freijedo, J; Moraes, M; Mallmann, M; Antunes, C ; Benfica, J; Vargas, F; Santos, M ; Teixeira, IC ; Rodriguez Andina, JJR; Teixeira, JP ; Lupi, D; Gatti, E; Garcia, L; Hernandez, F;
PUBLISHED: 2009, SOURCE: 10th Latin American Test Workshop in LATW: 2009 10TH LATIN AMERICAN TEST WORKSHOP

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TITLE: Delay modeling for power noise and temperature-aware design and test of digital systems
AUTHORS: Freijedo, JF; Jorge Semião ; Rodriguez Andina, JJ; Vargas, F; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 2008, SOURCE: Journal of Low Power Electronics, VOLUME: 4, ISSUE: 3

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TITLE: Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits
AUTHORS: Jorge Semião ; Freijedo, J; Andina, J; Vargas, F; Santos, M ; Teixeira, I ; Teixeira, P;
PUBLISHED: 2008, SOURCE: 14th IEEE International On-Line Testing Symposium in 14TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS

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TITLE: Power-Supply Instability Aware Clock Signal Modulation for Digital Integrated Circuits
AUTHORS: Jorge Semião ; Freijedo, J; Moraes, M; Mallmann, M; Antunes, C ; Rocha, L; Benfica, J; Vargas, F; Santos, M ; Teixeira, IC ; Rodriguez Andina, JJR; Teixeira, JP; Lupi, D; Gatti, E; Garcia, L; Hernandez, F;
PUBLISHED: 2008, SOURCE: International Symposium on Electromagnetic Compatibility in 2008 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC EUROPE)

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