Juan Jose Rodr?Guez-Andina
AuthID: R-00G-7AD
1
TITLE: Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits
AUTHORS: Jorge Semião ; Freijedo, J; Andina, J; Vargas, F; Santos, M ; Teixeira, I ; Teixeira, P;
PUBLISHED: 2008, SOURCE: 14th IEEE International On-Line Testing Symposium in 14TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS
AUTHORS: Jorge Semião ; Freijedo, J; Andina, J; Vargas, F; Santos, M ; Teixeira, I ; Teixeira, P;
PUBLISHED: 2008, SOURCE: 14th IEEE International On-Line Testing Symposium in 14TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS
2
TITLE: Enhancing the tolerance to power-supply instability in digital circuits
AUTHORS: Jorge Semião ; Freijedo, J; Rodriguez J R Andina; Vargas, F; Santos, MB ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 2007, SOURCE: IEEE-Computer-Society Annual Symposium on VLSI in IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES
AUTHORS: Jorge Semião ; Freijedo, J; Rodriguez J R Andina; Vargas, F; Santos, MB ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 2007, SOURCE: IEEE-Computer-Society Annual Symposium on VLSI in IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES
3
TITLE: Dynamic fault detection in digital systems using dynamic voltage scaling and multi-temperature schemes
AUTHORS: Rodriguez Irago, M; Andina, JJR; Vargas, F; Jorge Semião ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 2006, SOURCE: IOLTS 2006: 12th IEEE International On-Line Testing Symposium in Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium, VOLUME: 2006
AUTHORS: Rodriguez Irago, M; Andina, JJR; Vargas, F; Jorge Semião ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 2006, SOURCE: IOLTS 2006: 12th IEEE International On-Line Testing Symposium in Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium, VOLUME: 2006
INDEXED IN: Scopus CrossRef
4
TITLE: Dynamic fault test and diagnosis in digital systems using multiple clock schemes and multi-VDD test
AUTHORS: Rodriguez Irago, M; Andina, JJR; Vargas, F; Santos, MB ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 2005, SOURCE: 11th IEEE International On-Line Testing Symposium in 11th IEEE International On-Line Testing Symposium, VOLUME: 2005
AUTHORS: Rodriguez Irago, M; Andina, JJR; Vargas, F; Santos, MB ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 2005, SOURCE: 11th IEEE International On-Line Testing Symposium in 11th IEEE International On-Line Testing Symposium, VOLUME: 2005
INDEXED IN: Scopus WOS