José Carlos Alves Pereira Monteiro
AuthID: R-000-85F
31
TÃTULO: Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates
AUTORES: Sidinei Ghissoni; Joao Batista D dos Santos Martins; Ricardo Augusto D da Luz Reis; Jose Carlos Monteiro;
PUBLICAÇÃO: 2010, FONTE: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation in INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, VOLUME: 5953
AUTORES: Sidinei Ghissoni; Joao Batista D dos Santos Martins; Ricardo Augusto D da Luz Reis; Jose Carlos Monteiro;
PUBLICAÇÃO: 2010, FONTE: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation in INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, VOLUME: 5953
INDEXADO EM: 
WOS
WOS32
TÃTULO: Analysis of the Conditions for Worst Case Switching Activity in Integrated Circuits
AUTORES: Carlos Sampaio; Jose Monteiro; Silveira, L. Miguel;
PUBLICAÇÃO: 2010, FONTE: 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2010 FIRST IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)
AUTORES: Carlos Sampaio; Jose Monteiro; Silveira, L. Miguel;
PUBLICAÇÃO: 2010, FONTE: 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2010 FIRST IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)
INDEXADO EM: WOS
WOS33
TÃTULO: A New Quaternary FPGA Based on a Voltage-mode Multi-valued Circuit
AUTORES: Cristiano Lazzari; Paulo Flores; Jose Monteiro; Luigi Carro;
PUBLICAÇÃO: 2010, FONTE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010)
AUTORES: Cristiano Lazzari; Paulo Flores; Jose Monteiro; Luigi Carro;
PUBLICAÇÃO: 2010, FONTE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010)
INDEXADO EM: WOS
WOS34
TÃTULO: Integrated Circuit and System Design : Power and Timing Modeling, Optimization and Simulation. 19th International Workshop, PATMOS 2009, Delft, the Netherlands, September 9-11, 2009, Revised Selected Papers
AUTORES: José Monteiro; Rene van Leuken;
PUBLICAÇÃO: 2010
AUTORES: José Monteiro; Rene van Leuken;
PUBLICAÇÃO: 2010
INDEXADO EM: 
Openlibrary
Openlibrary35
TÃTULO: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
AUTORES: Lars Svensson; José Monteiro;
PUBLICAÇÃO: 2009, FONTE: Lecture Notes in Computer Science
AUTORES: Lars Svensson; José Monteiro;
PUBLICAÇÃO: 2009, FONTE: Lecture Notes in Computer Science
36
TÃTULO: Efficient Dedicated Multiplication Blocks for 2's Complement Radix-16 and Radix-256 Array Multipliers
AUTORES: Leandro Zafalon Pieper; Eduardo A C da Costa; Sergio J M de Almeida; Sergio Bampi; Jose C Monteiro;
PUBLICAÇÃO: 2008, FONTE: 2nd International Conference on Signals, Circuits and Systems in SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS
AUTORES: Leandro Zafalon Pieper; Eduardo A C da Costa; Sergio J M de Almeida; Sergio Bampi; Jose C Monteiro;
PUBLICAÇÃO: 2008, FONTE: 2nd International Conference on Signals, Circuits and Systems in SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS
INDEXADO EM: WOS
WOS37
TÃTULO: A comparison of layout implementations of pipelined and non-pipelined signed radix-4 array multiplier and modified booth multiplier architectures
AUTORES: Leonardo L de Oliveira; Cristiano Santos; Daniel Ferrao; Eduardo Costa; Jose Monteiro; Joao Baptista Martins; Sergio Bampi; Ricardo Reis;
PUBLICAÇÃO: 2007, FONTE: 13th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005) in VLSI-SOC: FROM SYSTEMS TO SILICON, VOLUME: 240
AUTORES: Leonardo L de Oliveira; Cristiano Santos; Daniel Ferrao; Eduardo Costa; Jose Monteiro; Joao Baptista Martins; Sergio Bampi; Ricardo Reis;
PUBLICAÇÃO: 2007, FONTE: 13th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005) in VLSI-SOC: FROM SYSTEMS TO SILICON, VOLUME: 240
INDEXADO EM: WOS
WOS38
TÃTULO: Gray encoded arithmetic operators applied to FFT and FIR dedicated datapaths
AUTORES: Eduardo A C da Costa; Jose C Monteiro; Sergio Bampi;
PUBLICAÇÃO: 2006, FONTE: 12th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003) in VLSI-SOC: FROM SYSTEMS TO CHIPS, VOLUME: 200
AUTORES: Eduardo A C da Costa; Jose C Monteiro; Sergio Bampi;
PUBLICAÇÃO: 2006, FONTE: 12th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003) in VLSI-SOC: FROM SYSTEMS TO CHIPS, VOLUME: 200
INDEXADO EM: WOS
WOS39
TÃTULO: Precomputation-based Sequential Logic Optimization For Low Power
AUTORES: Alidina, M; Monteiro, J; Devadas, S; Ghosh, A; Papefthymiou, M;
PUBLICAÇÃO: 2005, FONTE: IEEE/ACM International Conference on Computer-Aided Design
AUTORES: Alidina, M; Monteiro, J; Devadas, S; Ghosh, A; Papefthymiou, M;
PUBLICAÇÃO: 2005, FONTE: IEEE/ACM International Conference on Computer-Aided Design
40
TÃTULO: Low Power Architectures for FFT and FIR Dedicated Datapaths
AUTORES: Costa, E; Bampi, S; Monteiro, J;
PUBLICAÇÃO: 2003, FONTE: 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 in Midwest Symposium on Circuits and Systems, VOLUME: 3
AUTORES: Costa, E; Bampi, S; Monteiro, J;
PUBLICAÇÃO: 2003, FONTE: 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 in Midwest Symposium on Circuits and Systems, VOLUME: 3
